Differential pairs length matching in HDI PCB
antman , 03-25-2019, 11:15 AM
Hi Robert and everybody,
I am currently working over a layout of a board which integrates a DDR4-64 bits bank, and I have some doubts about length matching (this question can be extended to any differential pair). I have attached a image where you can see a example of differential signal, concretely the clock signal of DDR4. The match length of the Command - Address - Control signals is performed, but intra-differential pair needs to be corrected yet, with a difference between P and N of aprox. 1mm, and a goal tolerance of 0.1mm.
I have read a lot about length matching solutions in differential pairs, but I am not sure what can be the best solution to my problem.
The main question is where to place the matching length. There are three possible places: at the start (FPGA), along the track or at the end (1st memory). At the extremes, the advantage is that the impedance is constant during most of the travel, but the differential phase will increase, and therefore, the jitter and the common mode noise. If we match the signal along the track, where mismatch appears, we will insert points where the differential impedance change the value, and I think this also affects to signal integrity. What is your advice?
Regarding to the matching method, what do you think is better? Smooth Sawtooth or Strong Trombone?
Thank you very much!
I am currently working over a layout of a board which integrates a DDR4-64 bits bank, and I have some doubts about length matching (this question can be extended to any differential pair). I have attached a image where you can see a example of differential signal, concretely the clock signal of DDR4. The match length of the Command - Address - Control signals is performed, but intra-differential pair needs to be corrected yet, with a difference between P and N of aprox. 1mm, and a goal tolerance of 0.1mm.
I have read a lot about length matching solutions in differential pairs, but I am not sure what can be the best solution to my problem.
The main question is where to place the matching length. There are three possible places: at the start (FPGA), along the track or at the end (1st memory). At the extremes, the advantage is that the impedance is constant during most of the travel, but the differential phase will increase, and therefore, the jitter and the common mode noise. If we match the signal along the track, where mismatch appears, we will insert points where the differential impedance change the value, and I think this also affects to signal integrity. What is your advice?
Regarding to the matching method, what do you think is better? Smooth Sawtooth or Strong Trombone?
Thank you very much!
robertferanec , 04-01-2019, 06:35 AM
In most design guides you will find recommendations to correct the N/P difference as close as possible to the place where it occurs. The goal is to make the N & P edges travel together.
How to do it, so the impedance is not influenced, that is different problem. In most cases you will see number of small bumps on the shorter signal, which may change the impedance, but they still may keep the impedance in tolerance. However, I found out, that using small bumps will not really add much length and sometimes there would be so much bumps, that they would be on most of the track. So, often I only use one bigger bump (I have never had problems with this). If you like have a look at this my video how they do it: https://www.fedevel.com/welldoneblog...oller-hub-pch/
How to do it, so the impedance is not influenced, that is different problem. In most cases you will see number of small bumps on the shorter signal, which may change the impedance, but they still may keep the impedance in tolerance. However, I found out, that using small bumps will not really add much length and sometimes there would be so much bumps, that they would be on most of the track. So, often I only use one bigger bump (I have never had problems with this). If you like have a look at this my video how they do it: https://www.fedevel.com/welldoneblog...oller-hub-pch/
antman , 04-08-2019, 08:38 AM
Hi Robert,
thank you very much for your very interesting answer. I have also found more explanation at the end of your video.
I would like to share this link, where Dr. Howard Johnson calculates the reflection signal during a mismatch length.
Best regards,
thank you very much for your very interesting answer. I have also found more explanation at the end of your video.
I would like to share this link, where Dr. Howard Johnson calculates the reflection signal during a mismatch length.
Best regards,
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