USB C DP/DN lines length matching problem

[robertferanec]

Maybe have a look also at the TPS65982 chip. I am not sure if that could help (but it will probably add also cost and take some space)

[bremenpl]

Hi Robert, thank you for answer.
The example you have shown is indeed interesting, but I cannot math it 1:1 not only because as you mentioned it's a different connector, but also I only have 4 layers PCB (I dont route any signals in the GND and power plane). I also think that the amount of VIA's per connection in their USB 2.0 differential pair is not equal.

[robertferanec]

Yeah, USB C layout looks interesting.

Have a look also here: https://e2e.ti.com/support/interface...out-Made-easy#

I know, that your connector is different, but it is interesting to see, how they placed two VIAs on the USB 2.0 signals and how they swapped and connected them.

They also refer to TPS65982 "USB Type-C and USB PD Controller, Power Switch, and High-Speed Multiplexer" - maybe that could be useful: http://www.ti.com/lit/ds/symlink/tps65982.pdf

[Lakshmi]

Okay MCP2221A good option.
Yea Trace width is sufficient. Good Luck.

[bremenpl]

The USB IC

[bremenpl]

The trace is 13 mils. I dont predict higher currents drawn by this IC than around 20 mA. I have posted the schematics for that IC bellow.

[Lakshmi]

What's Current Consumption ?
What's trace width? looks like 10 mils
-Lakshminarayana K N

[bremenpl]

VCC = 3.3V

[Lakshmi]

VCC Voltage value near the USB pins ?
5V?

[bremenpl]

Ok, thanks for help!

[Lakshmi]

Yeah last one looks good.

[bremenpl]

Or this?

[bremenpl]

Lakshmi, those 2 elements connecting USB0 bus with USB bus are 22R resistors. The length matching is achieved within 0.5 mm error. Could you take a look at the new picture I have posted bellow?

[Lakshmi]

Since it's a Differential Signal you need to maintain the same trace space and length.(length is not achieved)
USB signal from the IC is going to Common mode choke (if am not wrong and then to the ESD right? ) From the CMC you could trace out from the right side instead from the left side so that you maintain the same trace length.

[bremenpl]

Is this better for the routing near IC?