Routing technique for 2 chips of DDR3

[Luca82]

Hello,
Usually the address/command/control/CLK of any DDR3 is routed in a fly-by topology (+ some write levelling to adjust skews).
When we have only two chips of DDR3 (4Gb each) to route (both on top as the microprocessor), I'm wondering if a T-branch topology would have an interest, since only two chips need to be routed (even if more effort than the fly-by topology).
Any ideas ?
Thanks a lot,
Luca.

[mairomaster]

I always use t-branch when routing 2 chips of DDR3. Probably most of the people do like that as well. Fly-by becomes more valueable for 4 chips.

EDIT: 500th post day

[Luca82]

Thanks a lot MairoMaster ! Do you see any major disadvantage in routing the two chips of DDR3 in a fly-by topology ?
Thanks a lot !

[robertferanec]

I'm wondering if a T-branch topology would have an interest, since only two chips need to be routed (even if more effort than the fly-by topology).

DDR3 can be definitely routed as T-branch if chip manufacturer recommends this (if not recommended or mentioned in the chip documentation, then be extra careful). T-Branch on DDR3 will work fine up to certain frequency - I know it works ok for 533MHz. I am not sure how much higher you can go ... also it depends on termination resistors (for higher frequencies, termination resistors are important).

Do you see any major disadvantage in routing the two chips of DDR3 in a fly-by topology

- You need termination resistors and voltage => more space, possibly also higher power consumption

EDIT: 500th post day

- mairomaster Thank you so much