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DDR3L rules and constrains confirmations

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  • Paul van Avesaath
    replied
    no layout survives first contact at least for me it doesn't

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  • Mihai
    replied
    Hi Paul van Avesaath,

    thanks for your input. Indeed, I am aware that increasing the length under the FPGA is not wise, as I may need that space for other signals, But I am trying different layout versions to see which is the best layout.

    I will give it a try with the chip rotated to 90 degrees.

    Cheers,
    Mihai

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  • Paul van Avesaath
    replied
    nice work!, but looking at it I do get te feeling you could rotate your ddr chip 90 degrees , this way your overal length will be shorter.. but I do not know if you have to board space to do this.

    also routing the length of one of your signal beneath the FPGA / uP is not a wise thing to do unless you do not have any other option.. this wil really restrict your rouitng options on that layer..

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  • Mihai
    replied
    Hi robertferanec et al,

    After about a 2 mouth pause I started to work again on this design. Please have a look the attached images, regarding the rooting and length matching for the ADDR and BANK0 signal. Is good practice to do it like this, I have respected all the rules DDR3 design?

    PS: it my first DDR3 design, the next one will be better.

    Cheers,
    Mihai

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  • robertferanec
    replied
    When you calculate crosstalk, there are more important parameters, not just clearance. Have a look here, it can help you: https://www.fedevel.com/welldoneblog...s-as-possible/

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  • Mihai
    replied
    Hi Robert,

    Many thanks for providing me useful informations.

    I have seen that the reset signal is not usually included in the lenght maching of the addr/ctrl/cmd group, however I seen that you are routing it toghether to have a close lenght, but with high clearance. We do not want to have some weird issues to do crosstalk. Should a 0.25-0.3 mm clearance be ok? I have done some calculations with Saturn and looks ok.

    I my design with a 800 MHz controller and 1666 MHz DDR3, I have established a clearance of 0.25 mm between each signals. I think this should cover all the clearance rules. I have included also the packagge delays of the controller in the lenght maching.

    Cheers,
    Mihai

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  • robertferanec
    replied
    In theory, you always can route the signals any way you want - you just need to know what you are doing.

    However, in reality, you may want to consider number of factors - for example, once you route signals from same group on different layers, you may be going into risk, that if you manufacture your PCB in different PCB manufacturers, you may get different results (I have seen this on some boards, because of I do not know ... a little bit different materials, or thickens, etc, ... do not forget, PCB manufacturer sometimes adjust stackup to meet impedance and if they change stackup thicknes or materials it can influence velocity and length of the signals - if you route all the signals same way, they will be influenced equally, but if you do not route them same way, they may be influenced differently).

    We sometimes route signals on different layers, you just need to be careful - have a look for example at JEDEC DDR3 memory module reference layouts, that can help you to get an idea how they do it (the reference layouts are free you just may need to register): https://www.jedec.org/

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  • Mihai
    replied
    Hi robertferanec,

    Following to improve the space usage on my DDR3 design I have found the following statement in vendor memory interface document (UG586_7series_MIS):
    "For fly-by routing, address, command, control, and clock signals can be routed on different layers but each signal needs to be routed consistently in one layer across all DRAMs. Any signal layer switching via needs to have one ground via within a 50 mil perimeter range."


    For me this means that I can route a specific signal from there on a dedicated inner layer, and other signal on other inner layer, am I correct? Or they refer to that all the signals need to be routed in the same way?

    Cheers,
    Mihai

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  • Mihai
    replied
    Hi robertferanec,

    I see, on my 8 layer stack-up the PCB company calculated the track widths to the have controlled impedance (50 ohm SE) to be 0.16 mm on the inner layers and 0.35 mm on top an bottom layers, I have redone the DDR3 layout over 10 times, to find a nice placement and a good pinout with low skew. Even thought the layouts were correct, I decided to make it again, and as expected with more iterations the layout looks better. I will let you know when I have a layout which ok for me.

    Cheers,
    Mihai

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  • robertferanec
    replied
    Yes, that is correct.
    PS: In the stackup document you can see the required track width for specific impedance on specific signal layer.

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  • Mihai
    replied
    Thanks Robert,
    So there are to keep the 50 ohm impedance for DDR3 on that specific layer right?

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  • robertferanec
    replied
    on both inner signal layers and the bottom layer with the same track width (~0.12 mm).
    - inner layers 0.12, outer layers 0.114

    Stackup is attached
    Attached Files

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  • Mihai
    replied
    Hi robertferanec,

    In your project OpenRex I see that you have routed the DDR3 interface, on both inner signal layers and the bottom layer with the same track width (~0.12 mm). This was the value which was required to route the tracks in order to have 50 ohm impedance for SE signals? Because in my case with 8 Layer stack-up (with 2 inner signal layers) the PCB company computed that I have to route with 0.16 mm tracks on inner layers and with 0. 35 mm on bottom layer. Or you have a custom stack-up with different dielectric thickness etc.?

    Cheers,
    Mihai
    Last edited by Mihai; 05-24-2019, 01:06 AM.

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  • Mihai
    replied
    Hi robertferanec,

    Indeed, the last few pins are extremely hard, you'll have to move existing tracks, vias etc to make space for them.

    Thanks,
    Mihai

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  • robertferanec
    replied
    Mihai, I would like to add, do not forget, routing 95% of BGA is simple, but last few pins can be extremely hard or impossible to connect. Be sure, you will be able to fan out the pins in the area where you route the memory signals - otherwise you may end up in situation when you will need to delete or re-do a lot of already finished layout. Have a look at our routing video, maybe it can give you and idea where to start: https://www.fedevel.com/welldoneblog...routing-video/

    Leave a comment:

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