GSM Noise and Signal Noise queries

[Mahsheed]

Hi,
1) With reference to my last post of GSM noise, I have designed my PCB with filters. I am attaching screen shots of power side of my PCB, if you can please check for any issues.

2) I am designing 4 layer PCB. On 2nd layer there is big ground polygon ( just like ground plane). Now on third layer there are sensative signals going below the Power polygon between the inductors. Since these signals are on third layer and are not directly under the inductors ( but under the VCC polygon on 4th layer), would these signals be effected? ( picture is attached for refference

3) Lastly, the signal tracks from Sim Card to GSM module are on third layer and on fourth layer, there is switching regulator and power polygons on top of it. Would these be effected? ( Again picture is attached for reference).

I will be highly indebted to you for this help.

[Mahsheed]

[Paul van Avesaath]

i think it looks ok, and i do not think your signla tracks will be affected by the smps as long as you have good grounding.

but please try and keep layout nice and neat... your via placement in the exposed pads is horrible.. align these..

if it looks good it will work good.. think of it as your signature, would scribble your name on this or use nice calligraphy letters
you seem to take care to make the schematics look good, do the same for you PCB.

[Mahsheed]

I have connected every ground pin directly to the Ground polygon in the 2nd layer with via (Separate via for each pin).

but please try and keep layout nice and neat... your via placement in the exposed pads is horrible.. align these..

Is it just that to align vias on the pads or anything else for layout? (I did not align vias on pads because these will be under the ICs :P )

Please have an eye on the attached picture, signals on 3rd layer are going between the two inductors on 4th layer. Is it safe?

[Mahsheed]

Hi Sir robertferanec ,
I am waiting for your final verdict. Thanks in advance.

[robertferanec]

Do you use blind VIAs? That can make your PCB much more expensive as it's necessary.

PS: Honestly, it is not easy to say from pictures how exactly it is connected, but if you used full GND, that could help (and that could also shield the signals on Layer 3 - I do that often)

[Mahsheed]

Yes, I used blind vias to minimize the size of the PCB. Actually I asked JLCPCB ( charges 13$ for 10 pieces of 4 layer) about blind vias and they said that they do not support it :P So I switched to PCBWAY( charges 49$ for 10 pieces of 4 layer). They support blind and burried vias. So yes the cost is increased, but keeping the size constraint, I can bear that cost.

PS: Honestly, it is not easy to say from pictures how exactly it is connected, but if you used full GND, that could help (and that could also shield the signals on Layer 3 - I do that often)

If possible, can you please quickly go through my pcb file? I can share it with you via email. I just do not want to have any mistake, as importing electronics to Pakistan is very difficult these days, so I can not take the risk of mistakes in my design.
I will be highly indebted to you for that.

[robertferanec]

- Blind VIAs: Ah ok, probably other parts of PCB are really busy. Just wanted to add, I always use through hole VIAs for powers and ground. Be sure you double check the blind VIA current capabilities and properties.

- Checking designs: I would love to help everyone who ask, however I am very sorry, I have a very long list of things what I need to do and simply there is not enough time. Even if I had a look at your board, I would not be able to tell you if it's going to work perfectly fine or not as many people has its own style for placement and routing and it would be definitely done a different way as I would do it. I am sure you understand.

[Mahsheed]

- Blind VIAs: Ah ok, probably other parts of PCB are really busy. Just wanted to add, I always use through hole VIAs for powers and ground. Be sure you double check the blind VIA current capabilities and properties.

Oh, I never thought in that direction. I am just wondering if blind vias have different current capacities than through hole vias. Since I am using the same dimensions of blind vias ( 0.3mm hole and 0.6 mm diameter).

Also, I have used multiple blind vias for power and ground tracks. I googled it, but couldn't find any significant current discussion of blind vias. What I found is that multiple small vias are equivalent to one large via (in terms of current capability) provided the equivalent cross section area is same.

[Mahsheed]

-

- Checking designs: I would love to help everyone who ask, however I am very sorry, I have a very long list of things what I need to do and simply there is not enough time. Even if I had a look at your board, I would not be able to tell you if it's going to work perfectly fine or not as many people has its own style for placement and routing and it would be definitely done a different way as I would do it. I am sure you understand.

Surely I can understand, your this help is of great value to us. Can you please check the attached picture, if the flux of two inductors on 4th layer have an effect on sensitive signals( not exactly under the inductors) on 3rd layer?

[robertferanec]

- Blind VIAs vs MAX current: I am not sure if there is difference. I would also expect similar max current if properties are the same as for a through hole VIAs, but just in case I would maybe double check with PCB manufacturer

- Signals directly under inductors: I do not do that.

[Mahsheed]

Oh, you mean if through hole and blind vias have same sizes, then it would behave similarly. Right?

- Signals directly under inductors: I do not do that.

No, Signals are not directly under the inductors. These are between the inductors and on the layer below to these. As shown in the picture last attached, signals are passing under the polygon that has attached two inductor's pads.

Will it still be an issue?

[robertferanec]

Mahsheed, I am not sure what to answer. I would not route critical or sensitive signals under or around inductors and under very noisy tracks / polygons. I am sorry if I did not answer your question directly (if what you have is ok or not) - honestly, I do not know.

[Mahsheed]

Mahsheed, I am not sure what to answer. I would not route critical or sensitive signals under or around inductors and under very noisy tracks / polygons. I am sorry if I did not answer your question directly (if what you have is ok or not) - honestly, I do not know.

Then would you suggest moving the sensitive signals on the ground layer (2nd layer) and placing ground polygon on 3rd layer ( just above those sensitive signals). In this case, signal tracks will be adjusted in the ground polygon ( by repouring it).
Or if you have any other suggestion, then it would be highly appreciated.

Also, would Rx, Tx be considered sensitive signals? O.o