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Dilemma, reroute all the board or only fix that

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  • Dilemma, reroute all the board or only fix that

    Hello all,

    i have a big dilemma about a board with:
    • imx6ull
    • nand mlc
    • sram
    • pmic
    In my opinion the board is routed in a very poor way. The board work but i have a problem in EMI emssioni. I have attached some image:
    1. Image1 as you can see the nand nets are wired on different layer so the length calculation in altium not consider that
    2. Image2 all the baord use VIA and not uVIA, this is not a big problem but i think it's possible to improve the routing using uVIA
    3. Image3 on the VIA 7V and 12V we have 1A of current flowing, the holes are 0.2/0.4mm i think the are small (despite they can support 2A from Saturn calculator with 20°C rise temp)
    4. Image4 seems like some holes are only thrown, maybe the fanout was done after the routing of the nets
    5. Image5 the point where i have the peak of EMI emission (on the TX_CLK of the ETH)
    My question is if in your opinion is better to redesign all the board from zero or only adjust the nets that generate EMI?
    What do you think?

    Attached Files

  • #2
    Hello ypkdani
    - The points 1) 2) 3) 4) may improve PCB, but I would say the main problem will be something else.
    - The 5) ... I would change that (I do not like to route critical signals in "circle") and I prefer to hide them inside of PCB.

    I just would like to point out, failing EMI can be for number of reasons and it doesn't have to be necessarily because of bad layout ... example I have seen boards failing EMI because signals going out of board were not filtered properly or because of multiple grounds or because proper power adapter was not used ....

    From my experience, good stackup can help (e.g. be sure you route signals by proper impedance e.g. 50OHM for standard digital signals, if possible place solid GND plane as close as possible under signal layer etc ... ). Also, EMC/EMI problems are often cause by switching power supplies (not proper layout, try to use shielded inductors, etc). Often, it is extremely hard to find what the real problem is - e.g. you may adjust a few nets on PCB, but you may still end up with problems.

    The simplest test is to manufacture the same PCB with more GND planes (possibly you can do some minor net adjustments) - if that helps. It is not ideal, but in some situations it really helps and it can work as a quick fix.


    • #3
      Hello Robert,

      Thanks for the reply. I m following your advanced PCB layout so comparing this PCB with your course indication I se many errors.
      For detect the EMI problem I had use a spectrul analyzed with a near field probes and find the point 5 as the main pick emission. Turning off the Eth port the emission disappear.
      So, re-net some signals maybe for now is the fast way to solve this main problem and plan a complete rework for the future to do a better work could be a good way in your opinion? I know that some risk remain



      • #4
        Turning off the Eth port the emission disappear.
        - that still may be stackup issue. If stackup is good, you should not see emission problem on bus - even if the bus is not routed perfectly.

        Also, from my experience, EMC/EMI is often much more complex problem and hard to debug - very often just switching off something or measuring 1 point and thinking we found the problem - very often it may be confusing and fixing that one thing will not solve the problem. Sometimes it does, but sometimes not (e.g. when you switch off ethernet, maybe you also lower activity on memory bus or power consumption goes down and power supplies are suddenly cleaner, etc ....)

        PS: are your memory tracks (and other digital signals) routed by 50OHMs? I see, that you have only one solid GND plane and other planes are quite broken ... what about return currents?


        • #5
          Hello Robert,

          yes the width of the nets are designed for match 50ohm but respect a GND plane, as you have seen there is only a solid plane (TOP with signals, GND plane, Signals + GND, Signals + GND, VDD planes, Bottom with Signals). As visible on the image attached the net ETH TX CLK pass on 5V, 3.3V and VCC_ARM_CAP (1.1V). Unfortunally i don't know how the return current flow ... there aren't stitching via near these nets vias, too .
          Every time i see this board i find new sources of problems so this is my dilemma if rework all the board from zero or hope to solve the problem with few improvements.

          Attached Files


          • #6
            What I would have a look at are also the tracks what are routed extremely close to each other. I am actually surprised the board is working reliably.


            • #7
              In fact is not working reliaby ... with some kernel command that read many data from the NAND we have problems that lock the device and you need to reboot that. Now we need understand the fast way to improve this board to solve the main problems... or redesign all the board. I'm tring to have some opinion, like yours, to take the better choise.


              • #8
                In fact is not working reliaby
                - in that case maybe complete redesign is actually a better idea than trying to fix the current design


                • #9
                  Hello all,

                  important update. Testing the circuit all the day to find the possible source of EMI radiation i have supposed that in my board the main problem is connected with the ETH1_TX_CLK signal. In my pcb i have a loop as in the image1 so i have bypass this using a small wire and i have discovered that the problem has remained . After many and many test where i have change the series resistence of this signal from 22ohm to 100ohm and adding 12pF at the micro output with poor result i have discovered somethink wery interesting.

                  In my circuit the clock is output from the micro, go in a serie resistance of 22ohm, travel in the pcb until a connector, this connector is connected to an other pcb, the signal travel into this second pcb and arrive in the PHY chip (KSZ8081). My emission peak is near the connector between the two pcbs. Today i have seen that, before enter the PHY chip, there i a 22pF capacitor on the clock signal to ground (image2).... removing that and doing a comparison measure, like in image3 keeping attention to mantain the same measure position, from -42dB of noise i have reach -53dB ...

                  My explanation about this is that this capacitor have generate a signal loop that have increase the EMI emission .... could this have sense?

                  Attached Files


                  • #10
                    That's fantastic!

                    PS: We often place PHY close to the CPU (so it would be on the same board with CPU).