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  • Custom Stackup & ImpedanceCalculation

    Hi Guys,

    I came up with a hard problem. I want to learn something about desiging a custom PCB stackup.

    Question1: In Figure-1 you can see the 4 layer stackup like this:

    L1. TOP - SIGNAL
    L2. GND
    L3. POWER
    L4. BOTTOM - SIGNAL

    I want to calculate the microstip 50Ohm and 100Ohm impedances on Top Layer. This is easy. I use Saturn PCB Design ToolKit -> Conductor Impedance Tab. In Figure1 prepreg thickness is 112um, which is 4.4mil.
    When I specify 7.3mil microstip and 4.4mil prepreg height, the impedance is 50Ohms. It was easy as I said before

    The problem becomes out when I want to calculate the Botttom Layer's impedance. I dont know how to determine the reference plane. Is it L3 Power plane, or is it L2 GND plane? If is it L3 I think the calculation is the same, But I think it must refence to the L2 GND plane. However the non conductive total thickness from L4 Bottom to L2 is 112 + 1180um = 1292um, 50mil. But 7.3mil track width makes 131 Ohms. Please tell me the true way. What is the reference plane ?

    The same problem can be seen in different stackups. I attached Figure-3 8Layer Stackup. When I want to calculate L3-SIG stripline impedance, what is the reference plane? Is it L4-PWR or L7-GND?

    Question2: Why there is different thickness of prepreg and core materials? This is standardized by IPC-4101B document or tested by IPC TM650.

    https://industrial.panasonic.com/con...eet_R-5775.pdf
    https://www.intel.com/content/dam/ww...e/an/an613.pdf
    http://www.eurotronics.be/documents/...data_sheet.pdf

    I have to design a board with has lots of SGMII(1.25Gbps) and a few QSGMII(5Gbps) interface signals. When I read Intel's design guide, it says over 10Gbps signals designers must choose low loss materials. Then I want to work with Panasonic Megtron 6 Core&Prepreg instead of ITEQ IT-180A. In the datasheet Page 4, 2116 sheet has 2 values of thickness which are 125um and 132um. I dont think 132um prepreg will become 125um after pressing or sandwiching to the PCB. How can I specify the correct value ?

    By the way when I look at IT-180A 2116 prepreg thickness is 4.6mil=116um. Panasonic Megtron 6 2116 prepreg 125/135um. Why are they different ? I can make you see lots of other materials (Isola vs.) which are totally different from each other.
    Attached Files
    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an613.pdf
    Last edited by ibocakir06; 02-06-2020, 10:57 PM.

  • #2
    Hi,
    Best people to answer your query re PCB Manufacturer.
    You need to consult PCB mfg and tell them you're requirements. They suggest which material to use and they will calculate the required impedance (through software).
    Yes s you go higher frequency material plays a very important role.

    For your first question, bout considering which ref plane: Usually, we rout impedance controlled signal on the top layer like 50Ohm. You may have to consider a D ref plane and calculate the trace width. Maybe Robert will guide you the right way here.
    As you go higher in Layer count like 6,8 Layer how you stack them up is matters. For eg., I've attached 6 Layer stack up for you and you can have a look at the trace width calculation wrt ref plane.

    Thanks.
    Attached Files

    Comment


    • #3
      Hi Lakshmi, Thank you for your answer example stackup.

      Originally posted by Lakshmi View Post
      Hi,
      Usually, we rout impedance controlled signal on the top layer like 50Ohm.
      I think you suppose that you place the component on TOP layer. If you design a double-sided PCB, when you place the components on the BOTTOM layer, you must route the single ended tracks 50 Ohm and 100Ohm differantial pairs.

      By the way, I think you didnt give the answer to the question 1 or 2

      Comment


      • Lakshmi
        Lakshmi commented
        Editing a comment
        Originally posted by ibocakir06 View Post
        Hi Lakshmi, Thank you for your answer example stackup.



        I think you suppose that you place the component on the TOP layer. If you design a double-sided PCB, when you place the components on the BOTTOM layer, you must route the single ended tracks 50 Ohm and 100Ohm differential pairs.

        By the way, I think you didn't give the answer to question 1 or 2
        When you say Double-sided PCB (assuming 2 Layer), keep in mind that Target Impedance is all w.r.t to the ref Plane. So for eg., If you're routing 50Ohm single-ended trace on Top Layer on Top Layer you must have solid GND ref plane/Trace right below the trace on the top Layer Similarly another way for the Bottom Single-ended trace. Hope this helps.

        For your first question, you usually consider GND as a ref plane (that's the best way you can also consider VCC as a ref plane). So if you're routing impedance controlled signal on the bottom layer you either consider L2 as ref Plane OR make sure you have solid GND trace/plane in the 3rd layer right below your impedance controlled signal. ( In one of my first board I had 90Ohm USB 2.0 signals that were routed in the top and Bottom-L4 layer, Stack up was: Signal, GND, VCC, Signal I considered trace width same as a top layer on the bottom layer as USB 2.0 isn't critical). It depends. Maybe @robert would correct If I'm wrong here.

        For your second question, 
        https://resources.altium.com/pcb-des...ampaign=buffer
        ​​​​​​​

    • #4
      I always design my PCB stackup the way, that the reference plane is the closest solid plane to signal layer. I do not think you can have L4 signal layer, L3 split power planes, L2 solid GND and say, that L2 is reference plane for L4. I believe reference plane needs to be a neighbor layer to signal layer, so fields between track and reference plane are directly created between these two layers. The kind of fields what we need can't be created between L4 - L2 if there are big chunks of copper on L3.

      Now, I said that many times in this forum - some power planes can be used as a reference plane, but not always (e.g. if you have many decoupling capacitors between GND and that specific plane, than it can be considered as reference plane ... or if signals are using that specific voltage e.g. 1.5V DDR power can be used as reference plane for ADDR/CMD/CTL memory signals, however, I would not use input power as a reference plane for local 1.5V signals). Also, power planes are often not solid and that kind of plane would not be a good reference plane (e.g. simply to say you need continues plane under the whole track to have a good reference plane, but it can be more complicated).

      About exact stackup, as Lakshmi suggested, I would talk to PCB manufacturer. They will tell you what PCB materials they use, I would not just pick up a material from internet, because:
      1) your PCB manufacturer may not have that material in stock and it will cost you a lot of money and time to get that specific material
      2) your PCB manufacturer have no experience with that specific material, so they do not know how it is going to behave during PCB manufacturing e.g. they do not know how much the thickness is going to be changed and how much all calculations need to be adjusted, etc

      Once you have materials, you can play with approximate calculations, but the final calculation needs to be done be PCB manufacturer

      PS: Why do you need different thickness? That will help you to achieve the track thickens you are looking for e.g. if you are using wider tracks (because you need cheap PCB), your reference plane needs to be further, if you need to use very thin tracks (because of high density design), reference plane needs to be closer.

      Comment


      • #5
        I'm really thankful for your attention. From your answers I understood that, in a four layer stackup(I gave above) we must route impedance controlled tracks on TOP(neighbour GND). If you need impedance controlled 2 layers, you must design a 6 layer stackup. (TOP-GND-SIG-PWR-SGN-BOT).

        I also understood the material issue. We must design the board colleteral control with the PCB manufacturing houses. The link Lakshmi shared is perfect.

        Comment


        • #6
          Hi again, I didn't want to create a new topic.

          I have to design a board at least 4 high speed signal layers, so I decided to use 10 layer stackup(according to info above ). Every signal layer(L1, L3, L8 and L10) have their own GND reference planes. However 2 power planes(L5 & L6) are adjacent each other. Is this a critical issue ?

          I am designing a SoM whose MPU needs [email protected] core voltage. I think L5 can be only +1.0V plane and L6 can be power split plane(+3V3, +2V5 etc.). For this reason, I need 2 power planes. What do you think about the stackup I gave here ? Before calculatiing the impedances, I wanted to ask you is this acceptable or not ?
          Attached Files

          Comment


          • #7
            Hi,
            May I know what kind of High speed design involves here? If It's not that critical you can stick to 8 Layer.
            Usually people try to keep PWR and Ground in near I mean Prepreg between PWR and GND.

            Comment


            • #8
              Actually I wrote above, lots of 1Gb Ethernet and a few QSGMII 5Gbps. I don't want to use 8 layer stackup beacuse of signal&GND reference plane relationship.

              Comment


              • #9
                I have used stackup like that in past (https://welldoneblog.fedevel.com/201...your-projects/) - but that was a very small board. If possible, maybe ask your manufacturer for bigger distance between power planes so noise on power planes are not transferred between them. However, I am not sure how thick Pregpreg they can use in that stackup between the power layers.

                Comment


                • #10
                  Actually my concern is about the EMI issue.

                  BTW, thanks for your example stackup. Where can I find more example stackups? Are there any websites or smt?

                  Comment


                  • #11
                    Good morning to everyone,
                    just to share those very nice video, in my opinion, about EMI and layers stackup.

                    https://www.youtube.com/watch?v=ySuUZEjARPY
                    https://www.youtube.com/watch?v=3Is7bra3tsc

                    Regard and have a nice day from Italy,
                    Luca

                    Comment


                    • #12
                      Hi again, I have designed a 10 layer stackup. I have attached here, someone can use it

                      I have also asked my manufaturer, they approved the core-prepreg thickness and impedance values.

                      Attached Files

                      Comment


                      • #13
                        Nice, thank you ibocakir06

                        Comment

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