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DDR3 Memory Layout - Data Strobe clock signals

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  • DDR3 Memory Layout - Data Strobe clock signals

    Hello All,
    During the DDR3 Layout a general practice is to have single ended traces as 50 ohms impedance and Clock signals to be 100 Ohms differential.

    My design has a controller with 100 Ohms differential source impedance and 120 ohms differential as Load impedance.
    Connecting these 2 with 100 ohms differential pair is causing reflections.

    Any thoughts?

  • #2
    robertferanec , In the open rex design also the controller source impedance is 100 Ohms, Trace are designed for 100 ohms but the memory IC impedance is over 120 ohms (Since the character input impedance is ~66 ohms for each pin of differential clock G3 and F3 as per IBIS model)

    You didn't had any reflection issues, did u?



    • #3
      Very often I see clocks to be routed with different impedance (usually between 60 - 100Ohms). I usually go with what is recommended in design guide or what is used in reference design or with closest impedance available on PCB. Of course for higher speeds (e.g. above 2.5GHz) you may need to be more careful, but for boards below 2.5GHz I have not seen any problems.

      PS: I have simulated some memory layouts, but usually diff clock is not a problem - usually I focus on address or data, these are more problematic.