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DDR3 Simulation - Cadence

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  • DDR3 Simulation - Cadence

    Hello
    robertferanec
    Administrator
    robertferanec ,
    I saw your video on DDR3 simulation and have some follow up questions:

    1. What is difference between Ideal and Non Ideal Power plane
    2. While setting the ADD/CMD signal only A0..A14 was selected, why A15 was not selected
    3. While setting the Ctrl signal only CS0 and ODT was selected and CS1 and ODT1 were not selected
    4. How to best select the Receiver or Driver(transmitter) IO model once the design is completed and the aim of simulation is to find out what could be wrong?

    Thank you.

  • #2
    1. I guess, you are asking when power plane can be reference plane. In many cases it can be for example when the signals running above/below power plane have same voltage level as the plane, or another example can be a power plane with many capacitors connected between GND and Power plane.

    2. I am not sure exactly what you mean, but in some designs not all address signals are used - depends on size of memory chips which are connected. However if A15 is connected between CPU and memory chip and if that signal is used, it should be also length matched together with other address signals. Could you tell me what video and what minute:second are you referring to?

    3. Again, depends on how memories are connected. I would recommend to have a look at different memory configurations and connections - google for words like slot (often there are two ranks/chipselects per 1 slot/module, but you can have more slots in one channel), rank/chipselect (usually more chips connected to the same bus, but only one is active), channel (usually another komplety separated memory interface), .... https://en.wikipedia.org/wiki/Memory_geometry

    4. For simulations I like to use a Wizard - that will ask you for settings of your design (e.g. controller, memories, etc). Then I use memory simulation tool - the tool runs all the kind of scenarios automatically (read, write, etc) and it will tell you what is wrong. Hyperlynx is good in this. PS: some time ago I made a video in Cadence about memory simulation: https://www.youtube.com/watch?v=-t25gJIDQNo

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    • #3

      Thank you Robert,
      I was also able to research more on these topics and few points from my side.

      1. During your simulation video, there was a point when you mention Ideal power plane and non ideal power plane.


      2. This point refers to when ADD/CMD are configured and A15 is not selected in the configuration @25:13 in your video
      The reason is the number of Address pins that will be used depends on memory type. For ex: in IMx6 board you have used 128Mx16 memory type.
      16 refers to the data bits and for 128M, the design uses 14 address pins (A0..A13) i.e., (2^14x8)/1024=128M (x8 here is used coz there are 3 bits for bank select and 2^3 =8, hence with 3 Bank select bits and 14 address pins the maximum value that can be addressed is 128M)
      if it were 256Mx16 the address pins required will be 15 (from A0..A14).

      3. Absolutely correct..

      4. The reason for this question is my design is ready and is failing the memory programming at times and I am redesigning it.
      Hence I am trying to take the parameters that the design is configured for and trying to get the simulation results for comparative study.
      In a nutshell, Reverse engineering the current design and finding the issues and then fixing the same with a before-after report.
      (*** it takes alot to get these parameters since it is distributed all over and not just limited to Hardware... :-D)


      Comment


      • #4
        1. Ideal power plane - I meant that the power plane can be used as reference plane

        4. Memory can be failing also due wrong memory controller settings, it doesn't have to be hardware. Often I initially use the same memory chips and the same memory controller settings as they used on reference design.

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