Stackup for a 6 layers PCB

[Victor]

Hi everyone,

I'm planing to design a PCB with a MPU and DDRs. I have some experience in 2 and 4 layers PCB and I think that this new step will be good for my professional carrer.

I want to use the new STM32MP1 and 2 DDR3 because in my opinion ST made a good work with the documentation that provides. I'm open to suggestions

I want to keep the price low, for that reason, first I checked cheap PCB manufactures that I normally use (OSH Park, PCBWay and JLCPCB) but 6 layer PCBs are more expensive that I thought in the firs moment. The only service I found that offers 6 layers + ENIG + Stencil for ~100€ is JLCPCB, the others are more than 200€.

But at the moment I checked the JLCPCB stakup for 6 layers I was confused.



My first thoughts was make something like this:
S
GND
S
---- Core
S
3V3
S

But with the JLCPCB stackup I don't know how to do it. In my opinion is a very estrange stackup but I don't have enough experience to judge it. Any suggestion?

Thank you very much.

[robertferanec]

- It should be possible - depends how much space you have. Especially, be careful, you do not want to run signals on L3 and L4 in parallel.

- Also, be sure you will know recommended track geometry (width & space) for this stackup and for the impedances you will need (e.g. 50OHM single ended, 90 a& 100 OHM differential). Some of these manufacturers do not provide these numbers.

- On your power layer you may want to have also memory power plane or GND plane in the area where memory tracks are routed

[Victor]

First of all, thank you very much for your answer Mr Feranec.

You are right, I forgot to check track geometry with this stackup. Making a quick calculation with a tool and taking in mind this stackup:
L1: S
L2: GND
---
L3: S
L4: S
---
L5: Power (I also forget to take in mind DDR power supply, thanks!)
L6: S

The results:


Looks like the width needed to achieve 50Ω impedance (1mm) are completely impractical for L3 and L4, right?

I suppose microstrip instead of stripline (anyway that L3 and L4 are inside the PCB) because reference plane for L3 is L2 and L4 isn't a reference plane. I'm right?
Maybe will be better consider it as an embedded microstrip, but as far as I remember differences are not very important in terms of impedance.

In summary, I should spend more money in the PCB to have a stackup that will make me the things easier.

I suppose that this stackup it's intended for something like that:
L1: S
L2: GND/Power
---
L3: S
L4: GND/Power
---
L5: GND/Power
L6: S

Right? But only 3 signal layers are not appropriated for me, in my opinion.

Thank you 😊

[robertferanec]

track geometry depends on how far reference plane is from signal layer - closer the reference plane is, smaller track you can use. So ideally you would like to have a stackup with small H (e.g. 0.075, 0.1 or 0.15mm are often used - depends on how expensive PCB you have)

[Luca]

If you do somenthing like this:

- L1 : Sig
- L2 : GND plane
- L3 : Sig
- L4 : PWR plane
- L5 : GND plane
- L6 : Sig

You can place STM, memory, and so on... on L1 (for example) and route critical traces on L3 | L1
Use L6 for other signals "less important". If you need some extra routing layers you can, with caution, use L4
I've used a lot this kind of stackp and work well but it's crucial to plan well the board, component placement and bypass caps especially if you place "fast silicon" on L1.
Don't forget also to fill with GND copper L3 and using stitching vias around the board for connect the GND plane.
Last but not least, if you need to change layer with different reference GND plane use as close as possible to this signals some GND stitching vias.
PS: JLC PCB works fine for the cost that you pay... but they don't allow blinded and buried vias

[Victor]

Hi Mr Luca,

Thank you very much for your comment. I already take into account this stackup but as I don't have any experience in DDR routing I thought that 3 layers are too few. But I have been investigating how many layers use this type of design:

Board	DDR ICs	Topology	Layers	Layers used for DDR
Freescale i.MX6 SABRE Board	2	T-Branch	6	4
Freescale Vybrid Board	2	T-Branch	8	6
iMX6 Rex Module	4	T-Branch	12	3
OpenRex	4	Fly-by (not sure)	10	4
STM32MP157A-EV1	2	Fly-by	6	2

In conclusion, it's possible. I will not discard JLCPCB stackup, I will continue investigating more about DDR routing

Doing this research I realized 1 thing:

• I always see DDR ICs placed in parallel and in front of the MPU (Figure 1), but ST reference designs are different, they put the 3 ICs in series (Figure 2). Why? Layout is easier?

One more thing, if I change the layout of the DDR, not the topology (T-Branch / Fly-by), only layers used to route, distance of the tracks (within the guidelines, of course), etc... This will cause me problems to boot the board? The calibration test is used to avoid this problem, right? I read this article that says that you should use the same memory IC to avoid problems and I'm starting to get paranoid 😄 Thank you!

[robertferanec]

- nice research
- fly by is easier for layout and can go up to higher frequency
- I also recommend to use the same chips as on the reference board as you can then use the same controller settings. However, once you know your layout is ok, you can use also other chips
- you can change layout, just be careful about groups being routed the same way (do not route signals from the same group on different layers) - that is safe way to do DDR layout.