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  • JLC2313 stackup with DDR3 fly-by


    Hi everyone,

    I’m building a simple SBC based on Allwinner A33 for my undergraduate final project, includes two x8 DDR3 chips. I’m going with 6 layers JLC2313 Stackup 1.2mm thickness (cost reasons). It’s my first DDR3 design and I have a lot of questions.😅😅

    Their website/field solver suggests 14 mil track on stripline and 5.7 mils on microstrip for SE50 ohms impedance. That’s super thick.
    1. I was wondering if I can use SE60 ohms and 120 ohms for differential pairs on DDR3 (That’ll be 9.4/3.8 mils).
    2. I’ve included the stack up. L1=> Signal, L2=> GND plane, L3=> Signal, L4=> Signal, L5=> Split Power, L6=> Signal. The prepreg (Dk=4.25) between L3 and L4 is just 5 mil (0.127mm) in thickness. Would that cause a lot of crosstalk? Was planning route ACC on L3 and data banks on L4. Would keeping almost minimum intersection (criss-cross) help me out here? I will reference it to the adjacent layers (GND,VDDQ), separated by cores with a thickness of 14.37 mil (0.365mm).
    3. Any suggestion on ddr3 layout and layer utilization, especially with JLCPCB’s 6L stack up? (Included a preliminary component placement).
    4. About DDR3 termination, BBB, most of the boards from Bpi, Olimex, OrangePi and even Rpi seems to be termination only the DRAM clock. What about ACC group? I’ve used NCT3101S VTT regulator. (Included schematics of the board, excuse the crudity, few things are yet to be added)
    5. DRAM reset signal, Should it be a pull up or pull down? Is it SoC specific? I’m using H5TC4G83AFR-PBA/PBC chips.
    6. I understand differential pair’s impedance can be seen as two single-ended TL’s impedance coupled with a gap. I’ve tried iCD stackup planner and can’t quite get the bang-on 120 ohms differential geometry right on JLC’s stackup (aware of the 10% tolerance), same story with their website( they seem to use Si8000). So, is it weird to maintain 60Ohm SE and 100Ohm Differential for DDR3 signals?


    I highly appreciate any inputs and suggestions.
    Thanks a lot


    Attached Files

  • #2
    hi i will try to help you,

    1)yes you can / may but you need to terminate to the correct values..(which is hard with ODT) if it is wise to do so NO, you will never reach the full potential / ddr3 speed of this board.. since it is you project I would suggest getting a better suited layerstack.. and at least 1.6mm which should not add a lot of cost.. FR408HR is a better but still affordable option then FR4
    2) you can do this with minimum issues if you do not run traces parrallel to each other for long lengths..
    3) keep signals that are meant to be togethor on the same layer.. e.g. data group 0 ( DQ0-7, DM, DQSp/n) on the same layer.. but the second group may be on another layer.. this also helps with creating room between the groups in your layout. keep the data (DQ/DQS/DM) signals mostly on layers 3/4 because those will be better impedance controlled. and use the outer layers for address and control.. because these are slower signals..(if you can fit them on layer 3/4 its better) and place caps underneath the ddr3's
    4) dont know should be indicated by datasheet.. i always terminate clocks, and address / control.. DQ's not because they are terminated by ODT.
    5) alsways check datasheet here.. it might differ from part to part.
    6) i suggest the saturn tool https://saturnpcb.com/pcb_toolkit/
    play around with it but do not limit you to the stackup.. go and see what other vendor options you might have..

    if you are doing it for the experience and will not really make the board.. go with another stackup.. otherwise see if other venders are available with different stackups.

    also a good thing is try to make you via's transparent in the impedance.. (with board cutouts in the power/gnd plane and a minimum of to gnd vias near the transition from one layer to the next.. especially for your ddr clock!

    good luck!

    Comment


    • #3
      1) I agree with Paul van Avesaath
      2,3) Better would be do data on L3 (referencing a lot to GND) and ADDR/CMD/CTL on L4 (refferencing a lot to Power on L5). If you use Fly-by, ADDR/CMD/CTL will be routed away from data.
      4) I also always terminate for fly-by (do not have to be terminated for t-branch ... but depends on frequency)
      5) see reference schematic (if you are not sure, put there both and leave not fitted)
      6) I do not know answers on this. I try to follow impedance ... especially for clocks and strobe signals on memory interface you never know what it can do. Probably only simulation could help you to answer

      I agree with Paul van Avesaath - try to follow other designs ... Even it may be more expensive, you have much higher chance it will work.

      Comment


      • #4
        Originally posted by Paul van Avesaath View Post
        hi i will try to help you,
        Thanks a lot Paul van Avesaath

        1)yes you can / may but you need to terminate to the correct values..(which is hard with ODT) if it is wise to do so NO, you will never reach the full potential / ddr3 speed of this board.. since it is you project I would suggest getting a better suited layerstack.. and at least 1.6mm which should not add a lot of cost.. FR408HR is a better but still affordable option then FR4
        Can you please suggest some cheap FR408HR based stackup, fab house that will get it done for around US$120? Mostly I was looking for 1.6mm PCBs from JLCPCB, but the track gets even wider around 21 mil for SE50

        2) you can do this with minimum issues if you do not run traces parrallel to each other for long lengths..
        3) keep signals that are meant to be togethor on the same layer.. e.g. data group 0 ( DQ0-7, DM, DQSp/n) on the same layer.. but the second group may be on another layer.. this also helps with creating room between the groups in your layout. keep the data (DQ/DQS/DM) signals mostly on layers 3/4 because those will be better impedance controlled. and use the outer layers for address and control.. because these are slower signals..(if you can fit them on layer 3/4 its better) and place caps underneath the ddr3's
        Sure, will follow this! Also, I was wondering if it's a good practice to copper pour empty regions on L3/4 to ground/VDD. Will this severely affect adjacent layer impedance?

        4) dont know should be indicated by datasheet.. i always terminate clocks, and address / control.. DQ's not because they are terminated by ODT.
        5) alsways check datasheet here.. it might differ from part to part.
        Will terminate ACC group and clock accordingly, ODT for DQ, DQS, DM signals. I found this: https://www.eevblog.com/forum/projec...-pcb-stack-up/

        Click image for larger version  Name:	owo 61.jpg Views:	0 Size:	54.8 KB ID:	14139

        Would this be true to any other memory controller that complies with JEDEC? Sadly Allwinner A33 datasheet doesn't have a detailed explanation.

        6) i suggest the saturn tool https://saturnpcb.com/pcb_toolkit/
        play around with it but do not limit you to the stackup.. go and see what other vendor options you might have..
        if you are doing it for the experience and will not really make the board.. go with another stackup.. otherwise see if other venders are available with different stackups.
        Will play around with this tool What are your thoughts about getting it done on a 4 layer? Everything on microstrip and maintaining the required 50,100 ohms impedance.


        also a good thing is try to make you via's transparent in the impedance..
        I'm sorry, didn't get that. Should I stitch vias at signal transitions for better return current? Probably have oval anti pads on differential vias. Mostly will be going only with through-hole vias, back drilling, buried/blind adds a lot of costs :/

        1) Going through some guidelines
        Click image for larger version  Name:	ddr3 .jpg Views:	0 Size:	29.2 KB ID:	14140

        The required net track length from the controller to DRAM and DRAM to DRAM. Would it be same on the inner and outer layers? Should i consider signal flight time? Compensate timing skew from escape routes?😅

        good luck!
        Many thanks and appreciate it Paul
        Last edited by grrmachine; 05-15-2020, 06:37 AM.

        Comment


        • Paul van Avesaath
          Paul van Avesaath commented
          Editing a comment
          sorry for my late reply.

          1 ) i am used to having discussions with an manufacturing company, not really the PCB manufacturer.. usually they have those contacts.. but getting these kinds of pcb's for such a low price can be difficult. espescially of you are planning controlled impedances. also they might differ from location to location.. china is you best bet here.. but to point a specific one.. i cannot.. keep in ind you will have additional start up fees for maunfacturing that will not be charged after your first prototype (unless you massively change your design) that alone is for me arounf 200 euro.. pcb price differs acoording to size and technology used (e.g. blind burried via's minimum trace width, controlled impedance, plating etc.etc.)also an FYI -> when using BGA's do not use HASL for your design.. always go with AU finish.

          2/3) yes and no.. it really depends on your design.. if you do not opt for copper balancing you might have to.. but be sure you make a lot of connections to GND because floating planes might cause more issues than that they solve. and yes you have to recalculate impedance if the distances of planes changes with regards to the tracks.. (better don't do that)

          6) it will be very tricky, because you also need solid power going to your chips.. a think a minimum of 6 is needed to get a proper design.

          transparent via design is making sure you via is not a to big impedance stub for your design. just google it.. you will be able to figure it out..
          https://www.intel.com/content/www/us...k1412632480254 (chapter 1.3.4)
          actually this is a very good document.. have a good read in this one (yes you need to add gnd via's to your layer transitions.

          the antipads are very usefull indeed and a must in high pseed design.. but thats also explained in that doc.

          its not that simple to design a good board.. it takes a lot of practise!

          if its a first time right then what have you learned nah i hope it all turns out.. best thign to do is Review your schematics and PCB alyout with multiple people and 9 out of 10 times you will find stuff to improve..

          just put some pics next time of your progress.. that is always interesting.

          hope this helps..

      • #5
        Originally posted by robertferanec View Post
        1) I agree with Paul van Avesaath
        2,3) Better would be do data on L3 (referencing a lot to GND) and ADDR/CMD/CTL on L4 (refferencing a lot to Power on L5). If you use Fly-by, ADDR/CMD/CTL will be routed away from data.
        4) I also always terminate for fly-by (do not have to be terminated for t-branch ... but depends on frequency)
        5) see reference schematic (if you are not sure, put there both and leave not fitted)
        6) I do not know answers on this. I try to follow impedance ... especially for clocks and strobe signals on memory interface you never know what it can do. Probably only simulation could help you to answer

        I agree with Paul van Avesaath - try to follow other designs ... Even it may be more expensive, you have much higher chance it will work.
        Thanks for the feedback robertferanec

        I' have a doubt about signal flight time and required net length. Which is mentioned in the previous reply, if you could give me some feedback and inputs that'll be helpful.
        It's my first DDR3 design and looking for multiple inputs to get it right the first time.

        Comment


        • #6
          The required net track length from the controller to DRAM and DRAM to DRAM. Would it be same on the inner and outer layers? Should i consider signal flight time? Compensate timing skew from escape routes?
          - for most of my designs, I do keep top/bottom part of signals similar, but ... I do not exactly match them. Worked oki for up to 900MHz

          Comment


          • #7
            transparent via design is making sure you via is not a to big impedance stub for your design. just google it.. you will be able to figure it out..
            https://www.intel.com/content/www/us...632494319.html (chapter 1.3.4)
            - Paul van Avesaath fantastic link! Thanks for sharing.

            Comment


            • #8
              Paul van Avesaath I shared your link on my linked in and people really like that link. I added your name into the original post, I hope it is ok: https://www.linkedin.com/posts/robfe...371240960-SlWT

              Comment


              • Paul van Avesaath
                Paul van Avesaath commented
                Editing a comment
                sure! thanks for sharing it! it's not mine but I hope some people can get good use out of it.. not too much or otherwise we will be out of a job 😊

            • #9
              Hi all,


              Sorry for the late response.
              robertferanec Paul van Avesaath Thanks for your inputs, and that's a great application note there.

              Sticking with JLC2313 but the setup now is S-G-S-G-S-G, and I can use 4/4.5 mil for 50 ohms. Click image for larger version

Name:	stackup s-g.jpg
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ID:	14665​Both the data banks are routed on L3. Bank 0 track length varies from 570 mills to 710 mils and 510 to 650 mils on bank1 Will length match them.


              Click image for larger version

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              Couldn't route all the signals in ACC to the first chip without using vias, Used layer 3 and 5 for to route ACC group.
              Click image for larger version

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              ACC on L5

              Click image for larger version

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              Layer 3 ACC

              Placed GND vias around signal transition, are they sufficient? DRAM clock over 533MHz is considered as OC (Allwinner's manual), not looking for anything above 667 :'D

              Click image for larger version

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              Here's Termination and DRAM CLK, Clock is routed on top layer and switches to L5 at 1st DRAM. I will calculate the required delay and match it to ACC. Before I run xSignals and length match the signals groups I had few things to clarify.

              1) I have a tight spot where an ODT signal crosses DRAM_CLK right through the via, but are routed on different layers. How bad is this?
              Click image for larger version

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              2) Using about 0.7mm dia anti pad and I was going through openRex layout anti pad is as big as the via pad. Should I follow the same, will have better reference around vias
              3) Should I put the data banks on a different layer? As there is no split power plane to deliver power, was saving that area to route power through thick tracks.

              I highly appreciate any inputs and suggestions! Also included PCBdoc!

              Many thanks!
              Nitin

              Comment


              • #10
                1) I do not route between diff vias
                2) Depends on PCB technology what we use, but often we use 0.1mm antipad (standard clearance), sometimes even less e.g. 0.075mm. The unused pads are usually removed from PCB anyway
                3) Why?

                Comment

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