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0.5mm Pitch eMMC Routing Issues

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  • 0.5mm Pitch eMMC Routing Issues

    Hi all, I have a question about routing 0.5m Pitch BGA Fanout.

    I have MTFC seires eMMC in my design. I want to make a fanout but the numbers are getting and getting smaller.

    Issue 1:

    Pitch: 0.5mm -> Ball Diameter: 0.25mm
    In my design, minumun drill size is 0.2mm.
    I dont want to decrease this number because of only one IC. Although if I use 0.15mm drill size, 0.3mm pad size via, the clearence is 2.998mil(Capture.png).
    However my min. clearance is 4 mil.

    Issue 2:

    I googled the problem, NXP has an article about this:

    4.3 Recommended 0.5 mm pitch BGA via fan-out pattern

    The pattern of centering the through-via within the four adjacent BGA land pads can not be used with 0.5 mm pitch BGA’s. This is due to the smallest through-via pad being too large to fit in the space available between the land pads. With a single trace routed between adjacent BGA land pads, the two outer rows of balls can be routed without a fan-out via. The two inner rows of balls must be routed to vias in the center area of the BGA and escape routed on other layers. An example fan-out of the LFBGA320 package is shown in Fig 6. See Table 5 for the layout tool design rules for 0.5 mm pitch BGA via fan-out.
    Issue 3:

    I found another document about eMMC routing. Octavo says that, you can route through NC pads.

    What dou you about Octavo's solution? Is it OK?

    I need your opinion. Thanks in advance.

    Attached Files

  • #2
    I would have a look how they did it in reference design.

    They may use VIA in pad to fanout, they may use super small VIAs, or as suggested, some footprints have space left for VIAs between pin rows under BGA, so you can use them.

    PS: I do not like to use these super small BGAs, but I know, sometime not possible

    PSS: Personally, I do not connect NC pins. I know some people do it.


    • #3
      Hi Robert, Thank you for your answer.

      I have seen only 1 board which has eMMC and uploaded one snapshot of it.

      Click image for larger version  Name:	Capture.PNG Views:	1 Size:	19.8 KB ID:	16552

      - They may use VIA in pad to fanout : They didnt use via in pad.
      - they may use super small VIAs : They didnt use small via. Dimensions: 0.2mm Drill, 0.45mm Pad

      They routed tracks with 3mil track witdth and 4 mil clearance. I also dont want to do like this.

      Do you mean, I can delete A7 pad route the track through it? Captured below.

      Click image for larger version  Name:	Capture2.PNG Views:	1 Size:	80.5 KB ID:	16553
      Thank you.
      Attached Files
      Last edited by ibocakir06; 02-03-2021, 11:37 PM.


      • #4
        The proper way to route it should be between pads. If you can't and there is no other option .... you can possibly get away with routing through a pad (I personally do not do that), but I would definitely not remove any pads (I am not sure how the melted ball would behave if there is no pad when the chip is soldered down)


        • #5
          OK Robert, I will not remove any pads, so all balls will be soldered down.

          However, you did mentioned about Octavo's solution. Can it be the other option ? I want to route through NC pins. NC means, as you know, Not Connected Internally. So, if you route smt through NC pins, electrically effect will not be on eMMC chip.


          • #6
            Theoretically connecting NC should not be a problem.

            - it may be a little bit of stub on signal,
            - also be sure that pin is not connected in future or in possible alternatives which you may use


            • #7
              I will route through the NC pins, Robert.

              Thank you for your great support


              • #8
                Hi again,

                I found Micron's document which says you can route through NC pins 🤗

                Please check it out !


                • #9
                  Thank you very much ibocakir06 for sharing


                  • #10
                    Hi ibocakir06

                    As others have mentioned, some eMMC manufacturers allow you to route through NC pins (the chips that I've used anyway).

                    However, there are times when this doesn't help because the pins you need are clumped together. e.g. SanDisk SDINBDG4-8G-1225.
                    In this case, I was fortunate enough to be routing on a high spec board that could have 3 mil traces on the external layers with a fairly tight clearance. This would have been enough to fanout the eMMC with microstrip tracks and drop down on vias as soon as I exited the IC. The trade off is that you have to implement a neckdown impedance profile. e.g. in my case, it would have fanned out with S54Ω and continues the route with S50Ω (set by the host).
                    You mentioned that you have to have 4mil clearance, but is there a way that this method can be an option for you?

                    In reality though, the smallest track I can have is 3.5mil and the tightest clearance is 4.5mil because I require the vias to be epoxy filled and capped.
                    The solution I had to implement was to allow the fabricator to misshape some of the pads in a controlled way. I had to ensure that all tracks were centred between pads. And I mean dead centre.
                    However, I genuinely don't like this solution. Although nothing went wrong, I don't believe that 20 boards are enough of a sample size to be making this decision for the final product.

                    On my next batch of prototypes, I have gone with a HDI layer stack which has increased the board cost, but has also opened up a lot of doors for other parts of the board.
                    This is probably a better solution than cutting pads. Does this method work for you?
                    just a heads up, HDI makes impedance control difficult. You need at least 2 ranks to keep your microstrip reference plane. If you use 3 ranks, one of those ranks would be wasted on a stripline reference plane unless you make that 3rd rank a signal layer like I did, in which case you have to worry about broadside coupling and can't have impedance control for a short section of the route. You still need to drop to an impedance controlled layer after the fanout.

                    I really hope this helps you. I understand your pain!

                    Please tell me if I'm wrong about any of these solutions.

                    Kind regards,


                    • #11
                      Hi Dan, thank you for your attention.

                      I have designed the as I mention above tiwh routing throudh NC pins and have sent gerber files to my manufacturer. My board was 100x180mm 8 layer and min clearance is 4 mil, min track is 4 mil and min drill is 0.2mm. I have only TH vias and this is not a HDI board, no microvias.

                      I think if I design a IMX8 Mini or Nano (0.5mm pitch), I would definitely use smaller vias or clearances. Only for eMMC fanout I did not want to decrase my values to 3 mil. I doubted about working or not with this method until I have found the Micron's document I shared above.

                      I am waiting my board to be produced and I will also share here it is working or not.



                      • #12
                        Hey, yeh sorry, I just kind of threw things at you in that last comment.

                        I almost used the IMX8 Mini. You can fan that out really well with just 0.2mm TH vias. NXP put a lot of effort into this and made a pretty good PCB design guide for it.
                        But I agree that you may need the smaller tracks and clearances. (although I haven't looked at it in a while).


                        • #13
                          I am very glad with your comments, pls keep going

                          To comply with IPC standarts I use 0.2mm drill size and 0.45mm via pad. I see someone use 0.2mm drill and 0.4mm pad, but I dont use like this. So you have to descrase the values.


                          • #14
                            Ah, I use 0.2mm holes with 0.4mm pads for my smallest TH vias because my preferred fabricators have proven that these dimensions are ok. But I guess that doesn't mean every manufacturer is ok with it.
                            If your requirements are tight enough, then you probably won't ever pick a manufacturer that can't do 0.2mm/0.4mm vias on a standard 1.6mm board.
                            Increase the board thickness and this will change because hole size is based on aspect ratio.

                            Which IPC standard are you referring to? My opinion is that a fair few of them are outdated. e.g. Manufacturers apparently used to have a problem etching right angle or acute angle bends because the etchant would destroy the corner. They can fabricate this now, even if it's still bad design practice for other more important reasons.


                            • #15
                              Click image for larger version

Name:	Capture.PNG
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                              This is I am referring.