High speed rule №5 in Advanced PCB Layout Course

[Rishat]

Hello Robert!

In the Advanced PCB Layout Course you tell us about HS design rule №5, which is «route signal groups by same topology». But when I opened OpenRex_V1I1 project, I saw that the DRAM_ADDR_CTRL group had been routed on two different layers at the same time — on layers L3 and L8. It seems it doesn’t follow the rule. Could you please explain this?

[robertferanec]

The rule is helpful for everyone who doesn't have much experience with memory layout - it is safe to use. If you know what you are doing, it can be broken.

[Rishat]

So you mean it's acceptable to route a DRAM_ADDR_CTRL group on two different layers at the same time but prohibited to do it with DRAM_BANK groups, right?

[robertferanec]

Theoretically you could route any signal on any layer, just you would have to be sure, that the delay is correctly calculated. But, that kind of layout would be too risky. You would not only need to have a very good software with accurate delay calculations, but also you wold have to be sure you have correct information about your stackup and your stackup will be always the same.

So, it is just much safer to route the groups on the same layers.

If needed, you can split the signals in the same group and some signals route one way and other signals the other way (as we did in the open rex), but I would minimize this technique - means, only use it when there is no other way to do it.

So, theoretically, you can do the same with DRAM_BANK group, but you may need to have a serious reason to do that and then you would need to be sure you do it correctly.

[Rishat]

I see. Thank you Robert.