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Setting via style for protecting power plane from a lot of unwanted holes

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  • Setting via style for protecting power plane from a lot of unwanted holes

    I have a high frequency transmission line and a lot of stitching vias near them. Because of these stitching vias on the signal layer (signal-ground plane-power plane-signal(ground pour)), power plane has a lot of holes and that can cause problem on the power delivery , current cant move easly on the power plane. So I want to use L1 to L2 via style (Blind 1:2 on screenshot) but I am not sure if this would have bad effect on the return path of the RF transmission line or would it have a some other bad effects if we look from RF point of view?
    Attached Files

  • #2
    Perhaps this video helps:


    • #3
      I am not expert for RF, but if I understand right, simply to say most of the filed would be travelling between track and GND, I would expect no difference in case you use through hole GND VIA vs uVIAs. Do you have any specific concerns why the signal should see it differently?

      I would also point out this video, maybe that can help:
      What Every PCB Designer Should Know - Return Current Path (with Eric Bogatin)


      • #4
        robertferanec I have already watched that video and that was a perfect video, I am really happy to see such quality videos thank you sir. I also think the same as you. Via style will not effect the impedance profile and I have no specific concerns in thinking that question I just want to be sure if this would have an effect.