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SDR SDRAM validation techniques

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  • SDR SDRAM validation techniques

    Hello all,
    In my design, I am using single data rate SDRAM memory attached to the DSP.

    Has anyone from the forum tried or can support me on finding IEEE standards or other methods to validate the SDRAM chip. I have looked for it, but could not find anything, only for DDR3/4, but not for SDR.

    So, if someone has encountered this issue, please share some thoughts on which docs, app notes
    or something, have to use as a reference.

  • #2
    What would you like to validate? Usually we run intensive memory test in different temperatures for hours/days on multiple boards to be sure memory is working oki.

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    • #3
      Hello Robert!
      I am want to validate it against some timing diagrams. Are not there some IEEE standards or Jedec you are aware of? For example the read or write functions are supposed to follow some predefined and standardized timings defined in some standards, depending on the type of memory, frequency and so on and so forth.

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      • #4
        For SRAM, it is often possible to measure it (with a good oscilloscope and if you have access to the memory pins).

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        • #5
          Hello Robert!
          I think it would be applicable also for Dram, but I am wondering what should I use as a reference to compare my results. So far I only have the data sheet, but will try to dig deeper,. In case there are no standards for this.

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          • #6
            Datasheet of the memory chip and cpu/mcu should describe the required timing parameters.

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