Routing Problems with a 8 bit Microprocessor Board

[Marco Ferrigno]

Good morning everyone!
I'm new to this forum. Let me introduce myself. I'm an electronic engineer who works as R&D Engineer for a small company. I'm mainly involved on writing firmware and developing algorithms for microcontrollers. Sometimes I route Pcb Boards for microcontroller applications (by OrCad Pcb Designer).
This time I'm involved in a PCB problem with a microprocessor (an 8 bit old one operating with a crystal of 26.045 MHz). My goal is to find a way to make this specific microprocessor board work. Let me explain better:
bout 2 years ago, in order to save money, my company decided to merge two complementary boards (both 4 layers) - which work fine since more than 20 years - into one. The new merged board was developed by a third part company. It has the same hardware than the two previous boards. After some basic positive tests and putting it in production we received, almost immediately, lots of negative feedbacks from the field. The board suddenly stops working due to unexpected random (and unknown) event. After other specific tests It seems that the bad event is caused by noise coming from outside the board and I'm strongly worried about an EMI problem. Excluding a problem on the firmware (it is the same than the two boards that works well since years) I decided to going back and look at pcb tracks.

This is a 4 layer board and I cannot identify a separation between Ground, Power and signals, maybe because of the high number of signals (address bus, data bus and many I/Os) and high density of components.

I have a lot of question obvously, but

I'm asking if someone can help me to find a book or a good course on the topic so that I can orient myself to route well the board for this specific application (data buses, address buses...)

Watching at some of Robert videos I saw that maybe 4 layers is not a good idea for this board (6 would be a better choice), so I'm deciding to route again the board with 6 layers instead of 4.

a) Can be the following 6 layers order considered a good choice (Rick Hartley on https://www.youtube.com/watch?v=52fxuRGifLU&t=2891s)?

- sgn/Power
- Ground

- sgn/Power
- Ground

- sgn/Power
- Ground

b) I understand that, in this distribution, every time a signal "jumps" from 1) to 5) or viceversa I need to put a Ground Via nearby in order to guarantee a good return path for displacement currents.
Am I right?

Every comment or idea for a better routing is really appreciated
I'll share with you any pcb image if necessary without any problem

P.S.
I know that the processor is an old one, maybe a good 32 microcontroller could do the job, but the company decided to still keep it for a while.

Thank you a lot

Marco

[qdrives]

I do not think EMI causes these problems as it generally is rare (for reasonable or better designs), unless they are working in an extreme EMI noisy environment (like welding robot). You could do some tests: https://www.youtube.com/watch?v=CxPy5Ehe0jI and https://www.youtube.com/watch?v=7r81MfHQyXI or https://emc.live/wp-content/uploads/...EMI-30-min.pdf

Same components and same firmware? And still 26.045MHz? With external memory it could be a timing issue. Look at the length of the traces, especially the clocks.

For the stack-up, it is not just the layer count, but the spacing between the copper layers.

[Marco Ferrigno]

Hi qdrives,
Thank you for your reply

I'm not sure if EMI is the real problem. The board is the brain of a lift controller, it is usually in an noisy harsh environment. It also drives some relè and receive some digital inputs from the outside
I'll do some other tests with a rele's coil in order to see if a bad event is catched, very good idea, thank you!

Yes, same components, same firmware and still 26.045MHz
Do you mean that is important to keep the same length of clock and buses being also sure that the memory timinig is ok for this application, right?

[qdrives]

One of the questions is perhaps more important: do you filter and handle the inputs correct - both in hardware and in software?
Memory is getting faster. Perhaps if the clock line is short compared to some other signal, the memory does the wrong action. This is not only for clock, but may also do be Rd/Wr and other control lines.

[Marco Ferrigno]

About filtering all I/O in hardware and Software I remark that circuits on the new board are the same than the two previous "separate boards", the software is exactly the same....
so maybe I need to compare the traces lengths

I'll check and let you know

[qdrives]

If the old design barely worked correct, the new layout could screw that up to the point that you notice it.

[Marco Ferrigno]

Hi,
I Built an electric arc generator. Putting it close to the board It seems that It works fine without problems.... Maybe it is not an EMI problem.

I'm going to compare buses lengths from each other comparing them also with control lines length too
I'm noticing, and I suppose it is not so good, that all buses and relative control lines have a loto of branches in order to reach vaiuous peripherals (ram, flash, PIO, etc...).

I'm also wondering:
With a 26.045MHz Crystal, how long a trace should be in order to avoid reflections phenomenas?
Considering c/f it should be fine because it should be < 11 m. I'm ok with this length for sure.

[robertferanec]

What helped me to find problems on several boards is Environmental chamber test. Try to switch on and run the board at -40C Deg - that helps to find interfaces running "on the edge" (they usually stop working or you may noticed errors). But of course, it can be also for example crosstalk or all the kind of other noises created by component placement or routing.

[Marco Ferrigno]

I took some measurements on address bus, data bus and control signals...
I think it is not good but fine. I put all data on a chart

[Marco Ferrigno]

Hi Robert!
Thank you for your suggestion. I'll try to find a way to perform a test at -40°C

I also noticed that soldering capacitors very close to the integrated circuits can change the behavior of the board in a worse way (the halt event became very frequent)

[robertferanec]

If you are not sure about memory bus stability, write and run a memory test. There are specific patters you would like to test, you can google for memory test code examples.

[qdrives]

robertferanec makes a good point with the memory testing. Unfortunately, that only works best with RAM memory as Flash is read-only.
For RAM there are many memory test. I have used March C- for my products.

For cold test you could use "freeze spray" - https://nl.farnell.com/c/chemicals-a.../freeze-sprays
For the hot test you could use a hair dryer or heat gun.

About the line lengths - I assume the lengths are in mils? So RD/ is 450mils and Flash CS is less than 50. You might want to increase the length of the control signals (RD, WR and CS) to be relative the longest.
Signals travel at about 150mm/ns (Er~4). Take the speed of the signal, distance difference and reaction time of the memories and you could estimate if this could be a problem.
This does require another layout and production cycle, so do all other tests first!


But you gave one important clue what seems to make it worse - capacitors. The power integrity of this design may not be good.
Are you sure that the voltage regulator is stable?
Some regulators cannot handle ceramic capacitors. Placing more of them (close to ICs) increases the instability.
Are you able to determine if the halt is pure hardware or perhaps a software interrupt (like hard fault) that stops the MCU's normal operation?
Do you have and use a watchdog?

[Marco Ferrigno]

Hi qdrives
The lengths are in mm

[qdrives]

450mm for the RD line!? That is something like 3ns.
Data lines vs WR is about 2ns difference.
How about signal integrity?
Why are these traces do long?
Inner layer our outer layer routing?

[Marco Ferrigno]

I know, it's a mess

The dimensions of the previous attached graph are the sum of all traces (buses and relative control lines) there are lot of branches in order to reach vaiuous peripherals...

- I ran a simulation with OrCad signal integrity, It seems not very good but it should works (signals rise or fall with some dumped oscillation, but after about 10ns remain stable)
The processor timing for read and write cycle is about 130ns and this can guarantee stable lines on buses and control lines during read and write processes (i guess)
- As I said before, the higher density and the high number of components could be the cause of so long traces. The overall board dimensions are 280 mm x 190 mm
- Routing is mainly on layers top, and inners layers. On bottom layer there is a ground plane (sometime interrupted by pcb traces).

Just to have an idea I attached a picture of the 280 mm x 190 mm board