DDR3 address pin swaping

[Reva_851]

Hello Everyone,
I have gone through the reference design of "Allwinner D1-H", which is the official design from Allwinner. In the interface of DDR3, they have swap addresses SBA0, SBA1, and SBA2 as well as the SWE signal of the MPU. I have attached the screenshot.
I do not have much experience in this field. I need your assistance to understand this.

[robertferanec]

They may use some kind of mirroring feature. I wrote an article on that topic some time ago: https://welldoneblog.fedevel.com/201...ng-pcb-layout/