two signal layers for one reference plan

[mor2810]

thank you all !!

[qdrives]

In a video by robertferanec (perhaps this one: https://www.youtube.com/watch?v=nPx2iqmVAHY) there were return currents on multiple layers.
I asked Heidi Barns (from Keysight) in a presentation (Altium Live) if that was related to skin depth.
In the power point she made it shows that the return currents are there at least for 1MHz on the THIRD gnd layer.

Not that I did high speed designs, but all my designs were 4 layer with only a single Gnd return 'plane' and no power plane.

[robertferanec]

I have never seen problems for interfaces like spi, uart, i2c using the same ground plane from two sides.

[mor2810]

anyone can help with that issue ?

[mor2810]

yes. for high speed it make sense. how "high speed" is related to the skin depth. at 1Ghz is 2um, 100Mhz 6.32u. while lets assume dielectric of 0.5OZ = 17um.
so for 100MHz and above you are correct, but what about I/O ? SPI/I2C ? which are at lower frequencies ? will this be a problem ?

[robertferanec]

I often do that. Very high speed signals have small depth (the currents will only flow on the surface, search for skin effect).

This video may help to visualize it: https://youtu.be/vrt3lL5gEb0

[mor2810]

i wanted to know if it is possible to use one reference plane for two signal layers without having issues with the return currents ?
if i have TOP - GND2 - SIG-PWR - GND5-BOT for example can TOP and SIG layers be reference to GND2 together ? cause when i think about it, there will be returning currents on GND2 for TOP layer and for SIG layer and they might cross each other or interfere with each other which can be dangerous for SI and EMI ? i never did that before (only had signal layer reference to its own GND).