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Hi everyone,
I am facing trouble with my motherboard again.
I succeeded in having it on 12 layers with vias 4020 for the smallest ones.
The previous version was based on 16 layers with vias 3615 and blind vias: I heard manufacturers shouting that it was not doable or ask for the amount of $85k for 5 prototypes.
Important to say it involved Megtron6 being a little afraid about the loss between MXM GPU and CPU (PCIe).
Megtron6 is very very very expensive and if you can get rid of it, it is a good idea.
After discussion with TI and following an article I found on the web and the length of the DPs of about 30 cm, I can use FR4.
I changed the stackup with a total height of 2,33mm, enlarged the gap for HDMI DPs in order to get a width of 90um.
So everything is above 90um including on BGAs I have with a pitch of 0.5mm and balls of 0.25mm.
I shared this last version yesterday with the first manufacturer.
Answer: NOT DOABLE!
You have to change your drills to 5030 because of the aspect ratio.
2.33/0.2 = 11.65 too high!
Wouaaaahhhhhh.....
I asked to another manufacturer the following questions:
If we consider 2 adjacent vias with different signals,
I would like to know:
- The minimal distance between the border of each via
- The minimal distance between the center of each via
- The minimal annular ring for each via
Drill holes: two cases: 0.2 mm and 0.3 mm
Answer:
For milling the distance is 200um from board edge to copper. However if the boards are in a scored panel then the space is 500um
For 0.2mm the distance is 400um for 0.3mm the distance is 600um
Minimum annular ring is 100um
OK I took 2 adjacent vias 5030 whose centers are distant of 600um, following what I was told.
The annular ring is 100um, OK.
The issue is that the distance between edge copper is 100um and not 200 um.
So there is an issue within the answer I got.
As you can see on the screenshot, the fanout of the CEX module is not obvious because you have DPs between DPs on other layers.
The spacing with the vias is better than 100um.
I cannot change the stackup because if I decrease the total height, the width of DPs will decrease too and go below 90um and perhaps 75um.
Under 75um, the manufacturers also shout.
Important to remember it is a 12 layers.
Except jumping into the river, what would be the options?
Thanks.
I am facing trouble with my motherboard again.
I succeeded in having it on 12 layers with vias 4020 for the smallest ones.
The previous version was based on 16 layers with vias 3615 and blind vias: I heard manufacturers shouting that it was not doable or ask for the amount of $85k for 5 prototypes.
Important to say it involved Megtron6 being a little afraid about the loss between MXM GPU and CPU (PCIe).
Megtron6 is very very very expensive and if you can get rid of it, it is a good idea.
After discussion with TI and following an article I found on the web and the length of the DPs of about 30 cm, I can use FR4.
I changed the stackup with a total height of 2,33mm, enlarged the gap for HDMI DPs in order to get a width of 90um.
So everything is above 90um including on BGAs I have with a pitch of 0.5mm and balls of 0.25mm.
I shared this last version yesterday with the first manufacturer.
Answer: NOT DOABLE!
You have to change your drills to 5030 because of the aspect ratio.
2.33/0.2 = 11.65 too high!
Wouaaaahhhhhh.....
I asked to another manufacturer the following questions:
If we consider 2 adjacent vias with different signals,
I would like to know:
- The minimal distance between the border of each via
- The minimal distance between the center of each via
- The minimal annular ring for each via
Drill holes: two cases: 0.2 mm and 0.3 mm
Answer:
For milling the distance is 200um from board edge to copper. However if the boards are in a scored panel then the space is 500um
For 0.2mm the distance is 400um for 0.3mm the distance is 600um
Minimum annular ring is 100um
OK I took 2 adjacent vias 5030 whose centers are distant of 600um, following what I was told.
The annular ring is 100um, OK.
The issue is that the distance between edge copper is 100um and not 200 um.
So there is an issue within the answer I got.
As you can see on the screenshot, the fanout of the CEX module is not obvious because you have DPs between DPs on other layers.
The spacing with the vias is better than 100um.
I cannot change the stackup because if I decrease the total height, the width of DPs will decrease too and go below 90um and perhaps 75um.
Under 75um, the manufacturers also shout.
Important to remember it is a 12 layers.
Except jumping into the river, what would be the options?
Thanks.
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