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HELP on DDR3 interfacing

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  • HELP on DDR3 interfacing

    Hi all. Could anyone tell of point to some documentation about ddr3 memory chips interfacing in order to understand how to obtain boards with same layout and different ram size combinations?
    I'll try to be more clear. If for example I have a 32bit capable ddr3 controller that accepts x8 and x16 ram chips for maximum 2 GB and lets say for example i need 1GB for my design...I have for sure 2 ways to reach the goal: use 2 x16 512MB chips or 4 x8 256MB chips.
    But could I use 2 x8 512MB chips and leave the option to mount the other two later to obtain different configuration
    (for example 2GB total ram)?
    If yes, is there a specific rule to observe in order to connect banks? Should I start from bank 0 then bank 1 and leave bank2 and bank3 disconnected?
    Any help would be much appreciated. Thanks

  • #2
    Hello sgufa, this may answer your questions: DDR3 layout vs Memory chip fitting

    You were not the first one asking this question, so I made a post. I hope you fill find it useful. Have a great day, Robert

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    • #3
      Thank you robertferanec. The point is where to find an exhaustive documentation about chip fitting and data bus because it's still not clear for me. From that example you made a 32bit configuration on a 64bit bus. Does it mean that you can run applications that need 32 bit addressing space? If so i suppose that in the case of a 32bit bus i could run only applications with 16 bit addressing space?
      Last edited by sgufa; 04-18-2016, 02:46 AM.

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      • #4
        Addressing is always the same (you only use the number of addresses based on size of your memory chips). Your schematic/layout of Address signals should be done for the highest memory chip you are planning to use (e.g. connect A0 to A15).

        When I was speaking about 64bit vs 32bit - I was referring to DATA bus. If you unfit a chip, you are dropping down number of data signals which you will be using.

        PS: I do not know any documentation about it, but I was not really looking.

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        • #5
          ok. now it's more clear. But I'll keep looking for a exhaustive documentation. Any help from anyone would be really appreciated.

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          • #6
            Hi,

            in DDR3 flyby routing, where we should place termination resistors, near end or far end?

            BR

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            • #7
              The far end, after the last chip in the chain.

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              • #8
                Hi, Thank you.
                Another related question is trace width and so trace impedance, 40ohm is recommended for DDR3 which require wider line, and it will make routing difficult. any idea?

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                • #9
                  40 Ohm sounds a bit low. What devices are you using? Is this value stated in the design guide/datasheet?

                  If you really need to achieve it and you don't have much space, you will need to let your manufacturer know that, so he can provide you with an optimised layer stack, which allows for thinner tracks. You can also consider using smaller vias if you can.

                  Of course, always think about if you are doing things the right way - often it happens that your idea about the layout is not very optimal and that is why you don't have enough space. This includes layers to be used, via use and placement, routing style, etc.

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                  • #10
                    Hossein_Karimiyan, have a look at our OpenRex project, this is routed by Fly-by. You can download the complete Altium project. It may help you. Here is the link >

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                    • #11
                      About the memory track impedance ... you can use both 40 or 50 ohms. Don't forget, then you need to adjust termination resistors and memory controller settings. Usually 40OHM is used for the boards with memory slots (e.g. SO-DIMM, DIMM, ...).

                      They both have advantages / disadvantages. E.g. for example here you can read "The lower impedance allows traces to be slightly closer with less cross-talk.", see: Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces

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                      • #12
                        Of course, always think about if you are doing things the right way - often it happens that your idea about the layout is not very optimal and that is why you don't have enough space. This includes layers to be used, via use and placement, routing style, etc.
                        Yep, I agree with mairomaster. Good layout is usually really hard to do! And by the end of the layout, when someone looks at your board they always say like - "That perfectly fits. There was exactly the space to route it " ... NO, THERE WASN'T! I HAD TO CREATE IT AND IT TOOK ME WEEKS!

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