Reducing risks on one-unit-only prototypes woth expensive SocS

[robertferanec]

What a beautiful board! Very nice.

[robertferanec]

Do not manufacture one unit - you want at least 3, ideally 5. You need more boards to compare the behaviour between them. Assembly process can bring tons of problems (bad soldering, bad component, misplaced component, wrong value component, ...) - and if you are unlucky and you build only one board with a faulty assembly it can take you ages to make it work.

If you do not use uVIAs, you should be able to get relatively "cheap" PCB (maybe up to 1000EUR?). Again, do not order 1 PCB, ask them to give you the maximum number of your PCBs which fits on the panel. Very often you can get 10 PCBs almost for the price of 3 (depends how big your PCB is and how big panel they use for manufacturing).

And, you really may want to buy new components - when you will be de-soldering parts, you may damage them and ... again ... you may spend ages by trying to figure out why something is not working.

I hope this helps.

[nachodizz990]

Thank you robert the estimated costs are exactly what you said lab circuit spain plus 85 each pcb mi idea its to solder all components at home but the ddr and bga by predefined mini stencilcs on a rework house
Whats your opinion

[robertferanec]

You do not need stencil for BGA, use some flux and heat them up (we use hot air gun). You may need a little bit of practicing, but we have done that million times it works oki. However, for you it may be better go to a rework house if you have this possibility.

Note: This is not BGA, but it is a very similar procedure (for BGA you do not need to put tin on the pads, just the flux):http://www.fedevel.com/welldoneblog/...a-hot-air-gun/

[nachodizz990]

Oh! thank you again Robert you´re a monster engineer!

I prefer to go to with a Rework House because they have XRAY inspection... haha

But i will try to do it further to save costs.

I hope for find a pcb house that offers cheap 12 layers with pre-defined standard stackup and without uVias

Somewhere i read that if it´s a new pcb its not neccesary to use solder paste as you said! Only flux
But if it´s not a new pcb with an unconfirmed value of tin left on the pcb also if you removed all the tin i´ts recommended to use solder paste

[nachodizz990]

I improved the component placing as you can see on the images and also routed almost all the board.

Due to the bad disposition of SoC ddr balls, i had to go with 12 layers but all trough hole vias.

I have 4 internal high speed signal layers but they are almost all empty excepting on the ddr3 area.I need one more power layer ...

I dont like this situation, my goal it´s to have a routing similar to the open rex ( it´s very nice) where all the layers are good filled

Would be perfect to be able to go with 10 layer

I´m planning to go for a bga 484 cyclone soc part instead od bga 672 reducing at the half the SoC price and may be the layer count ( i have to study all the bga io balls )
.

[robertferanec]

Fantastic progress

[nachodizz990]

robertferanec what can happen if i pullup the ethernet RGMII on the RNX9031 to the SOC 3V3 instead of pulling it up to the RNX9031 DVDDH that passes trough a ferrite bead?
Thank you in advance.

I´m trying to mathematically find the best RNX9031 decoupling scheme , i see your schematic, Terasic schematics and Texas Instruments Schematics and there are different.

I want to design my own board without copying to anyone.

The most easy to understand scheme it´s the Open Rex decoupling scheme ( 10 uf bulk, 100 nf cleaning after bulk and 10 nf at each pin) but i cant understand this approaches, i dont like to put decouplings without understand why these values are adecuate to my design

[robertferanec]

What is RNX9031? Do you mean KSZ9031?

[nachodizz990]

I´m evaluating if my power solution is the best choice for my design.I choosed this PMIC because it´s simple and cheap.

Actually i have a TPS65218 PMIC for 1.1V, 1.2V, 2.5V and 1.8V and two independent Bucks for 1.5V for DDR plus the termination LDO and another for 3.3 V for FPGA and IO

The TPS65218 PMIC haves 4 DCDC converters:

- DCDC 1, 2, 3 -> 1.8A max They generate 1.1 V - 1.2V for Processor System and 2.5 for Processor and FPGA
- DCDC 4 -> 1 A max It generates 1.8V for Ethernet and HDMI

In some development boards power blocks i see that 1.1V are rated for 3A and in others 6A ¿Are they crazy?

While running the altera Power Play Estimator (This Excel) i´m getting only 0.7 A required for 1.1V at full load










So i cant understand why the dev boards use 1.1V 3A DCDC SOLUTION


Just in case, i´m planing to change my power block replacing the TPS65218 PMIC by a TPS659037 solution (So much powerful and BGA )

Here the TPS659037 specs

One 0.7 to 1.65V at 6 A One 0.7 to 1.65 V at 4
One 0.7 to 3.3 V at 3 A
Two 0.7 to 3.3 V at 2 A
Two 0.7 to 3.3 V at 1 A
Seven General-Purpose LDO´s

Will my actual 1.1 V 1.8 A be suitable for A9 Dual Core At 924 MHZ ?

Thank you in advance !!

On the development board supplies schematics they have a total of 14 - 20 Ampsof total currents but the board is supplied with a 2A wall adapter

So i will desolder the inductors and measure currents with my Agilent U1273A at full loads, full- stressing the processor and FPGA

here´s nothing like real measurements !!

Here´s some strange

I think that a development board should be a reference design so overdimension of supplies are a WRONG WAY to do a reference board !!!

Maybe this is because they have the parts for free... I´m not !

[robertferanec]

Usually the high current regulators are used to cover current peaks. Also, sometimes the power is designed the way to get option to fit the most powerful pin to pin compatible chip or possibly next generation pin to pin compatible chips which you may not know about.

I am always very careful about powers and if I am not sure, I use power supply with at least the same maximum current as they used in the reference design. If you underpower a rail, the board may be occasionally crashing (or behaving unstable or weird) and you may not be able to find out what is causing the problem. Debugging this kind of issue is extremely time consuming and it can be very frustrating.

[robertferanec]

nachodizz990 I love your PMIC Schematic

[nachodizz990]

I´m a fedevel disciple! I copied the comment boxes from you, can you recognice it? and also the titles and also the decoupling under the rnx9031 .. the half of my board are a copy of your work so thank you in advance at september i will purchase a open rex and do the advanced for beacame profficient in DFA

[robertferanec]

Yeah Why to discover the wheel

[nachodizz990]

Sorry, i was mistaked ! The 1.8 Amp it´s really enought for the ARM A9 Dual core but i was forgetting that the FPGA also uses the same domain on shared mode ( is powered by the same 1.1V too) so i need at least 3A for 1.1V i will change PMIC!

I hope for someone can use my old schematic for doing a easy to use power solution, now i have to redesign the supply!

I´m using 5CSE without High Speed transceivers but the high end SoCs with high speed transceivers and a lot of logic elements need a peak current of 9A !!

Finally i go with two MAX17509ATJ a cheaper and most adecuate and powerfull solution removing the enpirion


robertferanec yo was right !

[mairomaster]

Are you sure you will have enough space for length matching the RAM?

[nachodizz990]

Guest thank you for your observation! but note that i have 4 internal layers for routing ddr due to de bad disposition of the DDR balls on this chip series. I tried once and i was succesfull now i´m starting from scratch again because i made a lot of changes but the next week i will start with DDR3 and i will be posting my progress, thank you for being interested

[robertferanec]

That is going to take some time to finish

[robertferanec]

Did you check if you can plug in a wide USB memory stick and RJ45 cable at the same time? Some USB dongles can be really wide: https://www.google.sk/search?q=usb+m...UIBigB&dpr=0.9

[nachodizz990]

Thank you robertferanec i will move the hub a little bit more to the front.

An important question i have it´s about the clocking, i´m generating ethernet, usb hub and phy (24mhz), and soc clocks from the Spread spectrum Clock Synthesizer (U9) and a 10 ppm oscillator. The usb chips are far away and i will route from synthesizer the 24 mhz clock to both chips in t branch, do you think that its better to place local oscillators on usb chips?