Announcement

**alazareff** · 08-10-2016, 07:57 AM

Wao a Cyclone V SOC with 2 DDR3 on 10 layers, very good job !!!!
I try a year ago to do the same for a module and it took me a lot of time to do it. The balls locations are not optimized. And the Terasic board are using something like 16 layers which is too expensive for me.
I finally did the layout with an 8 layers board for developpment purpose, but with 1 DDR3 chip. And since i have a potential business opportunity with an IMX6 i didn't launch the FPGA prototype.

Regarding the 24MHz, it is not that high compared to the DDR3 clock in T branch. Otherwise you can use a high speed buffer and connect the 24MHz to two inputs and use the 2 outputs to connect to each IC. And you should add 33 or 50 ohms serial resistors in case of.

One question : how do you plan to use the HDMI with the FPGA ? you already have a video IP and its Linux driver ?

**robertferanec** · 08-10-2016, 08:07 AM

nachodizz990 I mean, that the RJ45 and USB connectors may be too close to each other.

**nachodizz990** · 08-10-2016, 08:46 AM

Yes, robertferanec , youÂ´re right, Now I spaced the connectors, i supose that on almost all cases, the actual spacing will not be problematic, but i will try to space a little bit more

alazareff, yes, routing the ddr in 10 layers is a headache.But now if i design carefully the power distribution i will be able to go with 8 layers but i donÂ´t know if it worths ...

I think that altera expects that such a soc will be used on an expensive system and then with a lot of layers ...

The hard thing is that the DQS signals are in the middle of the chip, then matching the lenght of the dq was so hard

I simulated the ibis models from both memory and SoC and mi actual DQ routing seembs to be fine

I have a linux framebuffer for this but with a adv7123, buth the interface itÂ´s the same for the adv 7513

The fpga framebuffer uses the HPS DDR controller to access DDR trought the FPGA to HPS DDR bridge because the frames are so big at full hd.

For the wolfson i have an ALSA linux driver.

About the connection to the codec and hdmi itÂ´s trought the fpga fabric.

**nachodizz990** · 08-17-2016, 08:18 PM

robertferanec, mairomaster, iÂ´m up to end with ddr, finally 10 layers !!

- Now i only have to connect the SoC to the top of Fly-By trough Top and Bottom and maybe some signal trough L8.

- I developed the fly back block in a separate project and then i pasted it to the project.

- I will share the project with you soon!

- The data lanes are done, y placed DQS clocks lengths in the middle of the longest and shorthest DQ Bits, -5ps < DQS < +5ps

- Somebody can help me to port the proyect to xSignals for doing beter (easier) timing analisis?

- Forget the Planes, they are wrong xD

- I will place terminations @ beagle X15 style, i liked it

**nachodizz990** · 09-10-2016, 02:23 AM

Hi all I finished the DDR Routing

Now IÂ´m Getting crazy drawing the auxiliary power planes

Once again due that there are one voltage rail that connects only with 3 balls but there are on the opposite side of the soc iÂ´m very hungry xD

This is by far the more challenging to route SoC i ever seen

I want thank to robertferanec , mairomaster alazareff and all who helped me to take some decisions through the design flow, i will send you the project when i finish it

Also to the Fedevel Team for sharing their layouts and their work, I learned to make good layouts from you guys!

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