Announcement

Collapse
No announcement yet.

Reducing risks on one-unit-only prototypes woth expensive SocS

Collapse
X
 
  • Filter
  • Time
  • Show
Clear All
new posts

  • KingVita89
    replied
    You are right. Around 30-40 $ but maybe for prototype ok.

    Leave a comment:


  • robertferanec
    replied
    Do you know how much it costs? I think it is expensive.

    Leave a comment:


  • KingVita89
    replied
    Maybe for future this BGA adapter can be a solution.

    http://www.andonelectronics.com/prod...apters_40.aspx

    Leave a comment:


  • mairomaster
    replied
    Looks great, thumbs up!

    Leave a comment:


  • Nguyenvanhieu
    replied
    WOW.So amazing.Very huge topic.Junior hardware designer must try hard to do something like that.

    Leave a comment:


  • robertferanec
    replied
    very nice nachodizz990

    Leave a comment:


  • nachodizz990
    replied
    Here´re some pics more




    Click image for larger version

Name:	ssb3c.png
Views:	54
Size:	206.6 KB
ID:	4083 Click image for larger version

Name:	2.png
Views:	61
Size:	167.0 KB
ID:	4089 Click image for larger version

Name:	1.png
Views:	53
Size:	228.3 KB
ID:	4090 Click image for larger version

Name:	Sin título.png
Views:	47
Size:	292.0 KB
ID:	4093

    Click image for larger version

Name:	ddr.png
Views:	71
Size:	254.4 KB
ID:	4098
    Last edited by nachodizz990; 09-13-2016, 02:29 PM.

    Leave a comment:


  • nachodizz990
    replied
    Click image for larger version

Name:	g1.png
Views:	65
Size:	36.7 KB
ID:	4077

    Click image for larger version

Name:	g9.png
Views:	46
Size:	29.7 KB
ID:	4087 Click image for larger version

Name:	2.png
Views:	63
Size:	28.0 KB
ID:	4096

    Click image for larger version

Name:	g9.png
Views:	64
Size:	24.7 KB
ID:	4088 Click image for larger version

Name:	1.png
Views:	54
Size:	29.6 KB
ID:	4095


    Hi all I finished the DDR Routing

    Now I´m Getting crazy drawing the auxiliary power planes

    Once again due that there are one voltage rail that connects only with 3 balls but there are on the opposite side of the soc i´m very hungry xD

    This is by far the more challenging to route SoC i ever seen

    I want thank to robertferanec , mairomaster alazareff and all who helped me to take some decisions through the design flow, i will send you the project when i finish it

    Also to the Fedevel Team for sharing their layouts and their work, I learned to make good layouts from you guys!
    Attached Files
    Last edited by nachodizz990; 09-13-2016, 03:58 PM.

    Leave a comment:


  • nachodizz990
    replied
    robertferanec, mairomaster, i´m up to end with ddr, finally 10 layers !!

    - Now i only have to connect the SoC to the top of Fly-By trough Top and Bottom and maybe some signal trough L8.

    - I developed the fly back block in a separate project and then i pasted it to the project.

    - I will share the project with you soon!

    - The data lanes are done, y placed DQS clocks lengths in the middle of the longest and shorthest DQ Bits, -5ps < DQS < +5ps

    - Somebody can help me to port the proyect to xSignals for doing beter (easier) timing analisis?

    - Forget the Planes, they are wrong xD


    - I will place terminations @ beagle X15 style, i liked it





    Click image for larger version

Name:	cap.png
Views:	53
Size:	105.4 KB
ID:	3720
    Last edited by nachodizz990; 08-18-2016, 08:21 AM.

    Leave a comment:


  • nachodizz990
    replied

    Yes, robertferanec , you´re right, Now I spaced the connectors, i supose that on almost all cases, the actual spacing will not be problematic, but i will try to space a little bit more


    Click image for larger version

Name:	Sep.png
Views:	78
Size:	142.0 KB
ID:	3620


    alazareff, yes, routing the ddr in 10 layers is a headache.But now if i design carefully the power distribution i will be able to go with 8 layers but i don´t know if it worths ...

    I think that altera expects that such a soc will be used on an expensive system and then with a lot of layers ...

    The hard thing is that the DQS signals are in the middle of the chip, then matching the lenght of the dq was so hard

    I simulated the ibis models from both memory and SoC and mi actual DQ routing seembs to be fine

    I have a linux framebuffer for this but with a adv7123, buth the interface it´s the same for the adv 7513

    The fpga framebuffer uses the HPS DDR controller to access DDR trought the FPGA to HPS DDR bridge because the frames are so big at full hd.

    For the wolfson i have an ALSA linux driver.

    About the connection to the codec and hdmi it´s trought the fpga fabric.
    Last edited by nachodizz990; 08-11-2016, 08:21 AM.

    Leave a comment:


  • robertferanec
    replied
    nachodizz990 I mean, that the RJ45 and USB connectors may be too close to each other.

    Leave a comment:


  • alazareff
    replied
    Wao a Cyclone V SOC with 2 DDR3 on 10 layers, very good job !!!!
    I try a year ago to do the same for a module and it took me a lot of time to do it. The balls locations are not optimized. And the Terasic board are using something like 16 layers which is too expensive for me.
    I finally did the layout with an 8 layers board for developpment purpose, but with 1 DDR3 chip. And since i have a potential business opportunity with an IMX6 i didn't launch the FPGA prototype.

    Regarding the 24MHz, it is not that high compared to the DDR3 clock in T branch. Otherwise you can use a high speed buffer and connect the 24MHz to two inputs and use the 2 outputs to connect to each IC. And you should add 33 or 50 ohms serial resistors in case of.

    One question : how do you plan to use the HDMI with the FPGA ? you already have a video IP and its Linux driver ?

    Leave a comment:


  • nachodizz990
    replied
    Thank you robertferanec i will move the hub a little bit more to the front.

    An important question i have it´s about the clocking, i´m generating ethernet, usb hub and phy (24mhz), and soc clocks from the Spread spectrum Clock Synthesizer (U9) and a 10 ppm oscillator. The usb chips are far away and i will route from synthesizer the 24 mhz clock to both chips in t branch, do you think that its better to place local oscillators on usb chips?
    Last edited by nachodizz990; 08-10-2016, 06:26 AM.

    Leave a comment:


  • robertferanec
    replied
    Did you check if you can plug in a wide USB memory stick and RJ45 cable at the same time? Some USB dongles can be really wide: https://www.google.sk/search?q=usb+m...UIBigB&dpr=0.9

    Leave a comment:


  • robertferanec
    replied
    That is going to take some time to finish

    Leave a comment:

Working...
X