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Reducing risks on one-unit-only prototypes woth expensive SocS

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  • Reducing risks on one-unit-only prototypes woth expensive SocS

    Hi all, i want to collect some ideas or some usefull tips when designing prototypes with very expensive hardware such as Altera Arria, Cyclone or Stratix SoC Famlies in order to avoid waste much money on prototyping phases where a fail can be a big problem.

    I have fear to fail and I was thinking about a bga socket for example, so that if it works with the socket, further and without it, the integrity will be better or at least equal..., and if it fails i dont demage the SoC!, anyone has experience on prototyping with shuch systems?

    I think that i will not find a bga socket for Altera uBGA 672 Wire Bonded packages

    We´re designing a rangefinder embedded on a quadcopter with a lot of things and video transmit based on Altera soc family and i want to share the idea with you too !

    This block is able(tested) to catch a very high speed pulse without needing to have a some ghz logic, by detecting changes in the register.
    Perfect for a laser radar

    4 Pll with the same multypling factor BUT whith different phase shift feeding an 8 bit register when 4 of then are negedge sensitive.

    Thank you in advance!

    Attached Files
    Last edited by nachodizz990; 05-28-2016, 12:19 PM.

  • #2
    I have done a couple of designs with Altera Arria/Cyclone, no problems whatsoever. I can advice you to thoroughly test you design first on a development board to be sure: first it is working the way you want it to and second you have all interfaces that you can potentially need wired. Having a good FPGA engineer helps a lot as well.

    With the schematics/PCB check some reference designs from Altera, they have very good ones. The schematics should be relatively straight forward, however there are some small pitfalls which could be easily caught by reading the design guides. There is nothing hard with the PCBs - those FPGAs are big pitch devices so there shouldn't be any issues really if you are smart about it.


    • #3
      This is a big topic - and it is the main topic of Advanced Hardware Design course.

      When I design boards, I am also very careful. I pay everything from my own money. When building a prototype costs 10 000 USD I need to be quite sure, that the first prototype will be working oki (not saying that I also pay for months of development).

      I covered some topics in my blog:
      - x86 Motherboard Development Process – Step by Step
      - 8 Steps Schematic Checking Procedure
      - Checking your PCB from a Mechanical point of view
      - 10 Tips for Better Schematic Checking – Processor Boards
      - ...

      In your case. I have never used BGA socket, so I am not sure how reliable it is. And, I think the socket is very very expensive. If you follow reference designs you should not need the socket and you should just be fine. Be sure you check your schematic properly (our schematic & library checking often takes 2-3 weeks). In case something gets really wrong, you still will be able to rework the BGA chip.

      If you are not sure, do a lot of testing with reference boards - and then just create your schematic based on it. If you have to design your own small circuits, make 1 layer PCBs and test everything. You would be surprised how simple circuits will not work as you would be expecting


      • #4
        PD2: Robert you have to deal with semiconductor manufacturers to sponsor your boards as terasic does (it costs more for me the soc than the complete dev board) but i cant place a dev board in my final product you know..
        You are so popular i dont understand why they dont sponsor you ....

        It´s so difficult?


        • #5
          - Thank you

          - If you would need to re-flow a BGA for 4 times, then there is something wrong with the design.

          - none is sponsoring our projects. The managers of big companies see it different way All the projects and work we do is supported by people who buy our courses.


          • #6
            Yes i have to design with patience...
            Last edited by nachodizz990; 06-02-2016, 12:29 PM.


            • #7

              I modified the expensive power supply with a TI TPS65218 PCMIC, the other version was so powerfull but was about 28€ only the supply block, now is 4€ but i need too much power,

              Perhaps adding 2A buck regulator separately for 3v3 but they are so exensive...
              I will test the suply with some heat resistors and doing some tests to see their limits.

              I think that the most cheaper is to try designing my own buck ...
              I need some kind of soft start to chargue all capacitors that i will place.

              Anybody tested the PowerSoc ICS? en6360qa soo expensive too but 8 Amps...

              How is the performance of the OpenRex Pmic? , i choosed it because its a cheaper way, i will not use the i2c stuff, only the first time for burn the eeprom.Wold be fine to having a FLUKE thermal camera for observe the pcb heat stat...

              By last

              I´m not able to export a DIFF100 group to the layout editor, all it´s ok but it doesn´t appear as a class, only as a net on the PCB menu What I´m doing Wrog?

              Thank you in advance
              Attached Files
              Last edited by nachodizz990; 06-04-2016, 06:36 PM.


              • #8
                Can you provide some more information about what power rails you have, what ICs in total you need to power and how much current you need per rail.

                For the boards I work on, for the FPGAs we use only Enpirion modules, including EN6360 I believe. The modules seem to be very good quality - no problems at all. You are right that they are a bit expensive though. Different PMICs are often designed for specific processors and often can't supply to much current per rail, which might be required for the core rails of the FPGA.


                • #9
                  Of course!
                  More or less: pci xpress, ADV7511, wolfson audio, ddr on fabric and hps 512 and 1Ghz respectively, cmos camera with d phy adapter for csi,usb, an amazing ADC12J4000,ethernet,probably a wilink,its a vitamined version of the nano soc for my needs.
                  Now the problem is the fabric, 2 core niosII f at 145 mhz with freertos,plus the dual cortex A8, at 925 mhz perhaps with Qnx,so probably the only problem is the fabric because the remaining its similar to the rex for example...
                  Perhaps the pmic will be enaoght with some capacitance, soft start and good heatsink... I Think that the empirion is too big for this case.The fabrik is 50k Le's and i use almost all for video compressing and maybe OpenCL
                  Another problem is that i will put expansion headers .... I want to use the pmic but... Maybe i need to make an simple 2 layer board with the pmic part and make it twist to test limits,another problem its Reliability, if this board was being sended to neptuno i will be more relaxed with empirion... Haha
                  Last edited by nachodizz990; 06-02-2016, 05:37 PM.


                  • #10
                    As mairomaster noted, PMICs are usually very specific. They have a lot of outputs, but the maximum currents are very limited. In past designs I have used ISL6236A (same is used on the iMX6 Rex module). If needed, this can easily deliver 10A.


                    • #11
                      I upgraded the supply, thanks for your recommendations.

                      Schematic here:

                      1. 2. 3. 4. 5. 6. 7. 8. VCC5PROT. PMIC LINUX CTRL & MONITORING R10 value sets default startup voltajes for DCDC3 and DCDC4 R10 with a value of 95.3K sets: DCDC3 to 1.2v and DCDC4 to 1.5V. 17 19 18. R11 4.7K. X5R/X7R. X5R/X7R. R14 18k 1%. R17. IN_BIAS INT_LDO. 2 3. SDA SCL. R12 4.7K. 3 4 PB1 R13. ...
                      Last edited by nachodizz990; 06-17-2016, 07:55 PM.


                      • #12
                        Note the value of R14 R10 fail limit resistors is pending to set after testings compares with internal 800mv...
                        If someone sees any fail please comment it
                        Last edited by nachodizz990; 06-04-2016, 10:29 AM.


                        • #13
                          FINAL SUPPLY :

                          1. 2. 3. 4. 5. 6. 7. 8. VCC5PROT. PMIC LINUX CTRL & MONITORING R10 value sets default startup voltajes for DCDC3 and DCDC4 R10 with a value of 95.3K sets: DCDC3 to 1.2v and DCDC4 to 1.5V. 17 19 18. R11 4.7K. X5R/X7R. X5R/X7R. R14 18k 1%. R17. IN_BIAS INT_LDO. 2 3. SDA SCL. R12 4.7K. 3 4 PB1 R13. ...

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                          Last edited by nachodizz990; 06-09-2016, 10:23 PM.


                          • #14

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                            Almost Finished! Hope you like this !
                            Includes Cyclone V SoC and DAC38J84 full HDMI adv7513 etc...
                            Last edited by nachodizz990; 07-18-2016, 01:54 PM.


                            • #15
                              It looks very good Are you confident with everything already?