DRAM routing with LPC uC

[sashkoiv]

I'm working on my design where uC (LPC4357) and DRAM memory (AS4C8M16SA-7BCN) are used. I'm routing on a 9 layers. I have stakup as on the picture below. I'm using uVIAs, Buried VIAs and Through Hole VIAs. I have chosen Mid Layer 1 for routing the memory.
Could you recommend VIA style and comment the position of my memory according to uC. (I can not turn the uC because pads on the top are closed to their destination).
The thing that make me worry is small width of the PCB, it is just few mm more than the uC.
*I have marked control lines, data lines and address lines in different colors.

[robertferanec]

I am not sure what you mean by VIA style. You may need to discuss it with your PCB manufacturer. The VIA geometry what we normally use are: 0.27 / 0.1 mm for uVIAs and 0.45 / 0.2 mm for Through hole & Buried VIAs. These uVIAs have maximum length limit around 0.1mm, so that probably can not be used in your stackup.

Placement: try to do preliminary layout, but don't forget, you may want to keep data lines shorter than address / command / control lines. It's not clear from your picture which are data lines, but I think, it may be exactly the other way round.

[mairomaster]

Do you have a particular reason to use none-symmetric layer stack (9 layers)? It is not very typical, I would go for 10 rather. I also don't quite like the big thickness of the cores between layer 1/2 and 8/9. That will not really allow you to use micro vias, because of the small micro via ratio (1:1). It is better to speak to a manufacturer so they can recommend a suitable stack.

How many signal layers exactly do you plan to use to route the memory? Just Mid Layer 1 will not be enough by far I think. The width of the board and the orientation of the uC could also be a problem.

[sashkoiv]

I mean if it is better to use uVIA From the Top Layer to GND_Plane_1 and from there to Mid_Layer_1 as on the picture below or just Buried VIA from the Top Layer directly to Mid_Layer_1?
In recommendation from NXP they say that better to use as less as possible vias. I was looking for recommendation for DRAM routing but haven't found exactly for it. It is a lot of information about DDR3.

[sashkoiv]

mairomaster, concerning your comment - I don't have special reasons for this stackup.
I was thinking to use Mid_Layer_1 and Mid_Layer_2.
Concerning the orientation of the chip I'm agree, but other signals closer to their destination with this orientation. I can not change the width of the board because it is needed to keep the shape and size and this place is the only possible for placement so big component.

[mairomaster]

As I said, I don't think you can use micro vias between layer 1 and 2 with this particular stack up, since the core between 1 and 2 is 0.254 mm thick. For a micro via with standard aspect ration of 1:1, that would mean the via hole diameter would need to be about 0.254 mm, which is not a convention micro via (I don't even know if they can manufacturer such a big micro via). Micro vias normally have a hole diameter about 0.1 mm, which requires the separation between the two particular layers to be about 0.1 mm (+/- 0.05 lets say).

So the only option I can see is either to use Blind vias (it is blind, not buried) from layer 1 to layer 3 (Mid_Layer_1), or TH vias. I don't know what is the pitch of your devices, but both the blind vias and TH vias will occupy quite of bit of space, because they can't be that small.

[sashkoiv]

Thank you mairomaster and Robert for your answers very much!
First I'm going to do now is communicate to manufacturer about recommendation of nice stackup. In current stage of the PCB I can change it.
I really want to make good design!