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  • Help to decide vtt caps


    Schematic

    1. 2. 3. 4. 5. 6. 7. 8. HPS DDR3 A. A U8P. CV SoC Bank 6 (HPS) R57 100 1%. GND. HPS_RZQ D25. Net Class i HPS_DDR_A0 HPS_DDR_A1 HPS_DDR_A2 HPS_DDR_A3 HPS_DDR_A4 HPS_DDR_A5 HPS_DDR_A6 HPS_DDR_A7 HPS_DDR_A8 HPS_DDR_A9 HPS_DDR_A10 HPS_DDR_A11 HPS_DDR_A12 HPS_DDR_A13 HPS_DDR_A14. Net Class i DIFF_100 ...


    I will decouple VTT to VDD 1V5 but there is a lot of different opinions on this... xD another black magic topic ? its very funny

    Look at this

    Do you have problems of DDR3 VTT bypassing? This article examines this very query in specific details.


    http://www.freelists.org/post/si-lis...n-DDR3-DIMM,16


    I think that the placement its not optimal but its the only way to do it, should i replace the 100n with 220n or add more bulk?


    red = bulk
    green = resistor
    yellow = 100nf cap


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    Last edited by nachodizz990; 08-24-2016, 05:45 PM.

  • #2
    I am not saying this is bad or good, I would probably try to make it as a full plane rather than branches to keep the voltage in every point same or very similar. I am not sure how much, but branches may influence potential (voltage) distribution in different places of the branches and voltage may differ a little bit. Especially for VTT it could be visible due current peaks (you have there 24 parallel 47 OHM resistors). Also, in some designs they connect some VTT capacitors also between GND ,,, it may depend on what plane is reference to the tracks - if GND or VDD.

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    • #3
      Now i understand why you referenced vtt caps to both vdd and gnd, this is because L3 and L8 run between both planes.

      The common factor in this case is GND but a common sense approach should be to try to place 2 caps for each 3 terminated lines one cap for VSS and the oter to VDD

      As you said (another funny discussion):

      The main reason to decouple VTT is to provide a path for trace return current. If the traces have their return current on Vss, then it important to decouple to Vss. If traces have their return current on Vdd, then decouple to Vdd. And if return current is on a combination of both Vdd and Vss, decouple VTT to both ; -> http://www.sipiexchange.net/q?id=9168


      robertferanec , I modified the decoupling following your sugestion and also placed a VTT plane, now it looks much better , and about the 220 nf the best is to test the real board and then decide what is the most suitable value
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      Last edited by nachodizz990; 08-26-2016, 01:49 AM.

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