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satish2projects , 10-14-2016, 07:30 AM

Dear Sir,
I am satish kumar from India, I have subscribed your Advanced
PCB Layout course and completed. But while trying my own PCB design I got stuck-up at one point and cannot go further. So I kindly request you sir to solve my problem. Sir after following your high speed design rules I cannot understand at one point in Signal Integrity Issues. Whether it is required by importing IBIS Models or just following your high speed design rules may help without IBIS Models integration for any design. I cannot understand this Issue. And another problem is after integration
of IBIS Models I got error in Signal Integrity Analysis in Altium saying that there are lot of Reflections, Over-shoot and Under-shoot in my Design for DATA signals but there are no problems with ADDRESS Signals. I have followed good stack-up for pcb for 8-Layer Board and reached 50 to +/- 5% tolerance Impedance, but none of them worked.

Finally I have investigated schematic and came to a conclusion that Correct placement of 22 ohm Resistor is required between “ATSAM9G20 DATA signals” and “DDR SDRAM” as mentioned in the Application Note.
Sir, Today I have designed the ATSAM9G20 Board where the uProcessor is from
ATMEL. Luckily it has all good documentation and IBIS Simulation Files. But tomorrow if I want to design the High speed Layout for “ALL WINNER ARM-Cortex-A8” Core in which there are no IBIS Models provided for that Core, then What to follow. I have much confusion in that kindly help in this matter.
And another doubt is, what is the Rise Time And Fall Time of Processor for ATSAM9G20. They have not mentioned any Timings in Data-sheet. Where to get all this Information for Other Processor ARM-Cortex-A8 too. I have analyzed PCB Stack-Up in ICD Stack-Up Planner for 8-Layer Board. In application note page no:34 of ATSAM they have mentioned 75 Ohm Impedance for Signal and 15 Ohms for Planes but in ICD Stack-Up Planner I have Set to 50 Ohm Impedance +/- 5 % Tolerance Impedance. Which one should I follow?. I am bit confused. I am using BGA Package.
For DDR SDRAM is Length matching is required?. In some blogs in Internet I have seen that length matching is not required for DDR SDRAM is it Correct?.
Sir Kindly reply in this matter as soon as possible. I will be waiting most eagerly for your precious reply.
Thanking You Sir,
Regards,
B. Satish Kumar.

robertferanec , 10-16-2016, 08:41 AM

Hello Satish, if you are asking how to simulate, that is quite a complex topic.

1) If you follow design rules from your datasheet / design guide, you will be ok. If you do not have design guide, you may want to find a design guide for similar chip.
2) We only simulate if we have to break too many rules. Normally we do not simulate.

If I have to simulate, I do not use Altium simulator. You may want to go for something like Hyperlynx - it has memory wizard which helps you to simulate memory interface. For the simulations, you will need IBIS (or different kind of model). If you can not find simulation model, try to ask chip manufacturer.

To learn how to simulate, how to setup parameters and how to interpret results, you may want to search for a course or you may want to try to figure it by yourself, but it's not a simple topic. Really, it's something much more complex then can be described in a forum.

There can be many reason why is that. However, if everything is setup correctly, then double check your layout and connections. Do you use point-to-point connection (only two pins in net) or do you connect more chips together (then it depends how you do layout and route tracks). As you mentioned, series termination resistors may help.

I am not exactly sure how I could help you.

Some rules should be followed. Depends on frequency, number of chips, layout and how far they are placed from the CPU. Also, if you do length matching, be sure you do it correctly as SDRAM works differently comparing to DDR2/3. I would try to find a documents, maybe something similar to: https://www.micron.com/~/media/docum...ram/tn4614.pdf