Dear Feranec,
In Rex module PCB, i found net classes. but i didn't find a single rule which uses Net class as criteria. For example, DRAM_Bank1, Bank2, Bank,3 are classes. but these classes doesn't govern any rule.
checking all the signals is the only purpose to create classes, while reviewing?
Some times we need to define clearance between one class to another. How did you maintained in Rex module PCB?
i noticed that defining all relevant signal in one class have a purpose to check all signals while reviewing the final layout.
could you please elaborate it.
Regards
Meet
In Rex module PCB, i found net classes. but i didn't find a single rule which uses Net class as criteria. For example, DRAM_Bank1, Bank2, Bank,3 are classes. but these classes doesn't govern any rule.
checking all the signals is the only purpose to create classes, while reviewing?
Some times we need to define clearance between one class to another. How did you maintained in Rex module PCB?
i noticed that defining all relevant signal in one class have a purpose to check all signals while reviewing the final layout.
could you please elaborate it.
Regards
Meet
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