Crystal Layout
TiagoPereira , 10-22-2015, 09:34 PM
Hi Robert, i'm working in my final Project course for the university, and I have some doubts for routing some signals. So please tell me your suggestion,
The first doubts I search a lot but not find a reasonable response for this, what the best layout for crystal oscillator, when used a solid GND plane inner layer. I use two oscillator, one for HSE (8Mhz) and other for LSE (32.768Khz).
The second is, when routing differential pair and have restrait for minimal track width, for reason costs, what is the best practice to improve them.
For finsh, the signals like clock for spi up to 45Mhz, i2c clock, what is the minimal gap for others signals tracks? It's the same approach you explained about crosstalk (rise time, Substrate Height, etc..) ? And it's batter trace this signal in inner layer or outlayer. Or for this signs is not very important, about cross talk.
This is my project, and i'm very grateful because your PCB course, and all your videos help me make this possible.
The first doubts I search a lot but not find a reasonable response for this, what the best layout for crystal oscillator, when used a solid GND plane inner layer. I use two oscillator, one for HSE (8Mhz) and other for LSE (32.768Khz).
The second is, when routing differential pair and have restrait for minimal track width, for reason costs, what is the best practice to improve them.
For finsh, the signals like clock for spi up to 45Mhz, i2c clock, what is the minimal gap for others signals tracks? It's the same approach you explained about crosstalk (rise time, Substrate Height, etc..) ? And it's batter trace this signal in inner layer or outlayer. Or for this signs is not very important, about cross talk.
This is my project, and i'm very grateful because your PCB course, and all your videos help me make this possible.
robertferanec , 10-23-2015, 01:03 AM
1) Place the crystal as close as possible and keep the tracks as short as possible. If you are not sure, you can google for "PCB Layout Recommendations Crystal"
2) I am not really sure what do you mean. Geometry of differential pair need to be calculated based on your stackup and should take minimum track width into consideration. Maybe you need to recalculate your differential pair track width and gap or possibly change stackup?
3) I always try to keep bigger gap around clock signals (usually as big as possible) - if you are not sure, I would go for 5H as the minimum gap (H is the distance from reference plane). We always try to route all the important signals (like clocks) inside PCB and between two solid grounds planes.
I am very happy the course helped you
Your 3D models look fantastic!
Example: Screenshot from one of our boards - Crystal routing
2) I am not really sure what do you mean. Geometry of differential pair need to be calculated based on your stackup and should take minimum track width into consideration. Maybe you need to recalculate your differential pair track width and gap or possibly change stackup?
3) I always try to keep bigger gap around clock signals (usually as big as possible) - if you are not sure, I would go for 5H as the minimum gap (H is the distance from reference plane). We always try to route all the important signals (like clocks) inside PCB and between two solid grounds planes.
Examples of minimum track clearance
I am very happy the course helped you
Your 3D models look fantastic!
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