Hi people,
I am designing a board with a Cyclone V FPGA (672 BGA package), it contains 2 hardware memory controllers (HMC), onto each I would like to connect 2 128MB x 16 DDR3 SDRAMS. The DDR3 controller in the Cyclone V does not support write levelling, but I have noticed that a number of designs are using successfully fly-by routing topology anyway. What are the design considerations when using the Cyclone V with DDR3 sdram and fly-by routing topology without write levelling, I would appreciate any information on this matter. I would prefer fly-by over T topology, just because of less complex routing.
Thanks
herbx
I am designing a board with a Cyclone V FPGA (672 BGA package), it contains 2 hardware memory controllers (HMC), onto each I would like to connect 2 128MB x 16 DDR3 SDRAMS. The DDR3 controller in the Cyclone V does not support write levelling, but I have noticed that a number of designs are using successfully fly-by routing topology anyway. What are the design considerations when using the Cyclone V with DDR3 sdram and fly-by routing topology without write levelling, I would appreciate any information on this matter. I would prefer fly-by over T topology, just because of less complex routing.
Thanks
herbx
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