Experiences with CyconeV FPGA, DDR3 and fly-by routing topology

[herbx]

Hi people,

I am designing a board with a Cyclone V FPGA (672 BGA package), it contains 2 hardware memory controllers (HMC), onto each I would like to connect 2 128MB x 16 DDR3 SDRAMS. The DDR3 controller in the Cyclone V does not support write levelling, but I have noticed that a number of designs are using successfully fly-by routing topology anyway. What are the design considerations when using the Cyclone V with DDR3 sdram and fly-by routing topology without write levelling, I would appreciate any information on this matter. I would prefer fly-by over T topology, just because of less complex routing.

Thanks

herbx

[mairomaster]

I've done a Cyclone V design using t-branch. I even did termination to VTT with R-packs, which increased the complexity (not sure if it's really necessary and might get rid of it). I don't think it's such a big deal, especially if you don't terminate.

If the FPGA doesn't support write levelling I don't know how do they deal with the fly by. Does it say anything in the documentation?

[herbx]

@mairomaster, basically they say go with t-branch. But information I came across recently stated that with just two chips topology makes no difference.

[robertferanec]

I know, some FPGA chips have a memory calibration code which you can run to get the values for delays. I was not searching much, but maybe something like that exists also for cyclone: http://www.alteraforum.com/forum/showthread.php?t=53488

[herbx]

@robertferanec, thanks I was aware of this link and the Quartus external memory interface toolkit which can be used to measure the margin after calibration.