Global decoupling

[tuv0k]

Hi guys,

For CPU board design(mostly BGA packages) on which approach you rely on, global or local decoupling?

[robertferanec]

Number of capacitors and values: I use what is recommended in design guide or used in reference schematic
Placement: small values as close to the pins as possible (usually in the area under the pads), larger values around the BGA, largest values in path of the current flow.

[tuv0k]

What do you think about keeping interplane capacitance evenly distributed along whole board? I've seen couple of EMC guys doing it that way and claiming there is no difference if distance between GND and VDD plane is greater than 0.5mm...

[robertferanec]

Do you have a link to an article about it?

[tuv0k]

Do you have a link to an article about it?

http://electronics.stackexchange.com.../134978#134978

This guy holds a lot of EMC/SI instruction around the world. With good low impedance on the whole board you can safely switch routing layers even on 4 layer board and be confident that there won't be ground loops.

On the other hand, Henry Ott in his book claims that the best way is to place capacitance near the crossing via, but you need to know signal frequency first so you can dimension capacitor properly. I will add few thoughts about that on this post if I find them somewhere.

ADD#1:
"The location of the decoupling capacitors is not critical because their performance is dominated by the inductance of their connection to the planes. At the frequencies where they are effective, they can be located anywhere within the general vicinity of the active devices [1]."
http://learnemc.com/decoupling-for-b...s-power-planes
http://learnemc.com/decoupling-for-b...-spaced-planes

http://www.hottconsultants.com/techtips/decoupling.html

[robertferanec]

"The location of the decoupling capacitors is not critical because their performance is dominated by the inductance of their connection to the planes. At the frequencies where they are effective, they can be located anywhere within the general vicinity of the active devices [1]."

In some cases I do place decoupling capacitors further from chips (e.g. decoupling capacitors around memory chips), but I have never seen any problems with placing capacitors close to the pins. Maybe if you have some special limitations and for some reasons (e.g. space) you can not place decoupling capacitors close to the chip, you may want to try to simulate your board or go deeper into the problematic, but in general designs I believe placing decoupling capacitors close to the pins is just simple way to be sure it will work ok.

I am still not 100% sure what do you mean by "keeping interplane capacitance evenly distributed along whole board", but if possible I try to have a solid GND plane placed as a neighbour layer of a solid power plane (e.g. 3V3). I read in some articles, that it creates a capacitor which may help filter the power.

[tuv0k]

You most certainly won't have issues if you place decoupling capacitors near pins, it can't harm. But if IC's on board are 100MHz or more, there is no need to do it that way. However, I agree with you, I will also choose safe option - decoupling near pin with keeping in mind about layer capacitance.