Length match for Same Net
meet , 09-18-2017, 05:56 AM
Dear Team,
Can you please help to understand how can we length match two routes of a signal, which are separated from via.
During memory fan-out, i place a via as shown in picture, to route top and bottom memory signal. I see the total length of the signal. using the via, top and bottom layer memory chip is connected in top and bottom layer. if top layer trace is 10 mil than how can i make bottom layer track of same signal 10 Mil
Can you please help to understand how can we length match two routes of a signal, which are separated from via.
During memory fan-out, i place a via as shown in picture, to route top and bottom memory signal. I see the total length of the signal. using the via, top and bottom layer memory chip is connected in top and bottom layer. if top layer trace is 10 mil than how can i make bottom layer track of same signal 10 Mil
robertferanec , 09-18-2017, 08:24 AM
In Altium, this is tricky. You may need to measure the track manually (select part of the track which you would like to measure, go to Reports -> Measure Selected objects)
meet , 09-18-2017, 11:12 PM
Thank you robert for reply.
But how to make those two traces length match... using length matching command or still manually. i didn't find the hint in vedio
But how to make those two traces length match... using length matching command or still manually. i didn't find the hint in vedio
meet , 09-19-2017, 02:21 AM
Hi Robert,
in context to above post, i started to route memory signed manually. I was quite successful.. i used the command "Shift+H" . with this command i can see the instantaneous track length. Also with this command, i get the total net length including via. to eliminate this problem, i made the PCB width as 0 in stack up manager and which can be retrieved later.
in context to above post, i started to route memory signed manually. I was quite successful.. i used the command "Shift+H" . with this command i can see the instantaneous track length. Also with this command, i get the total net length including via. to eliminate this problem, i made the PCB width as 0 in stack up manager and which can be retrieved later.
robertferanec , 09-19-2017, 05:14 PM
awesome 
vietzung , 02-01-2018, 10:23 AM
Hi Robert,
I'm learning hightspeed design from your lesson,
In the lesson 2,
I understand that, all the nets in the DRAM_A[15..0] route manually, track by track.
in the picture 1, when i route in the top layer leng of track = 2.514 mm,
how i can route the track in the bottom layer with the length same in the top layer?
Do you have anyway? Another way different to "Interactive Length Turning"
Thank you.
I'm learning hightspeed design from your lesson,
In the lesson 2,
I understand that, all the nets in the DRAM_A[15..0] route manually, track by track.
in the picture 1, when i route in the top layer leng of track = 2.514 mm,
how i can route the track in the bottom layer with the length same in the top layer?
Do you have anyway? Another way different to "Interactive Length Turning"
Thank you.
robertferanec , 02-06-2018, 09:44 AM
I did it manually - interactive length tuning. I knew what should be the length, so I was watching the length and adjusting the track. Luckily, you only need to do it once - then you can always copy and paste it.
vietzung , 02-06-2018, 06:12 PM
I understand,
Thanks Robert
Thanks Robert
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