Hello,
I'm designing a camera module based on the Python1300 from ON Semiconductor. It is a 6-layer PCB (signal-gnd-signal-signal-pwr-signal) and my question is about the placement of the decoupling capacitors required for the image sensor.
In my design, the image sensor is on the bottom layer and the decoupling capacitors are on the top layer because all the space around the image sensor is used by a large lens holder.
The image sensor has several power pins Vdd_18, Vdd_33 and Vdd_pix and their associated ground pins.
I uploaded two screenshots of my PCB design.
Until now, my understanding to place the decoupling capacitors was that the current must flow through the big cap first then the smaller caps. For example, it should flow through the 100 uF, then 4.7 uF, then 1 uF, then 100 nF. However, I did not find any easy way to follow this rule when the decoupling capacitors are on the other side of the PCB.
By placing one via very close to the power pin of the image sensor, it seems to me that it is the optimal via placement to reduce the path inductance between the power pin and the capacitors.
However, should I place more vias all around decoupling capacitors? Should I also find a better placement for all those caps to get them closer to their dedicated power pins?
Please feel free to make comments and suggestions.
Thank you in advance!
I'm designing a camera module based on the Python1300 from ON Semiconductor. It is a 6-layer PCB (signal-gnd-signal-signal-pwr-signal) and my question is about the placement of the decoupling capacitors required for the image sensor.
In my design, the image sensor is on the bottom layer and the decoupling capacitors are on the top layer because all the space around the image sensor is used by a large lens holder.
The image sensor has several power pins Vdd_18, Vdd_33 and Vdd_pix and their associated ground pins.
I uploaded two screenshots of my PCB design.
Until now, my understanding to place the decoupling capacitors was that the current must flow through the big cap first then the smaller caps. For example, it should flow through the 100 uF, then 4.7 uF, then 1 uF, then 100 nF. However, I did not find any easy way to follow this rule when the decoupling capacitors are on the other side of the PCB.
By placing one via very close to the power pin of the image sensor, it seems to me that it is the optimal via placement to reduce the path inductance between the power pin and the capacitors.
However, should I place more vias all around decoupling capacitors? Should I also find a better placement for all those caps to get them closer to their dedicated power pins?
Please feel free to make comments and suggestions.
Thank you in advance!
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