PCB setup for BGA and DDR3

[michaelchang]

To make tracks thinner, you will need to place your signal layer closer to the reference plane (use thinner dielectricum and ideally you would like to have signal layer to be a neighbor to the reference plane). Also, I agree with mairomaster, if I had to use 8 layer stackup, I would try to go for Sig-GND-Sig-PWR-PWR-Sig-GND-Sig stackup. However, normally I do not use 8 layer stackup, because organization of layers is not very optimal.

You can make fully through hole BGA <-> DDR3 layout. Have a look at our OpenRex project - it is open source and you can download the Altium files: http://www.imx6rex.com/open-rex/

Thanks Robert. I need to re-consider the stackup.
The OpenRex project is really a good example and reference to our project, thanks for sharing.

[robertferanec]

To make tracks thinner, you will need to place your signal layer closer to the reference plane (use thinner dielectricum and ideally you would like to have signal layer to be a neighbor to the reference plane). Also, I agree with mairomaster, if I had to use 8 layer stackup, I would try to go for Sig-GND-Sig-PWR-PWR-Sig-GND-Sig stackup. However, normally I do not use 8 layer stackup, because organization of layers is not very optimal.

You can make fully through hole BGA <-> DDR3 layout. Have a look at our OpenRex project - it is open source and you can download the Altium files: http://www.imx6rex.com/open-rex/

[michaelchang]

Thanks for your feedback.

Previously, I planned to use the stack up with: sig-GND-PWR-sig, sig-PWR-GND-sig, in order to make GND and PWR closer. But I also wanted to make more signal layers refer to GND, so came up with that asymmetric stackup.

40 Ohm single-ended and 80 Ohm differential impedance are specified by processor's datasheet for DDR3 interface. Hopefully, I can get trace thinner by choosing an more appropriate stackup.

Well, let me try TH vias on my first BGA and DDR3 layout. ^_^

[mairomaster]

Your stack doesn't make much sense to me, it would be better to go with: Sig-GND-Sig-PWR-PWR-Sig-GND-Sig. That way L1 and L3 refer to L2 GND. Also L6 and L8 refer to L7 GND. That way you have 4 signal layer with ground reference.

0.5 mm track width is ridiculous for such signals. Do you have any particular reason not to go with the standard 50 ohm impedance for the single ended tracks? That will allow the track width to be smaller. Also I have the feeling that they used L7 for a ground reference in this case, which is quite far away from L5. That's probably why they ended up with such width.

It's should be very easy to do the routing with TH vias only if you have only one chip of DDR3.

[michaelchang]

Hello,

I am new to BGA and DDR3 layout. Currently, I am in a project with a BGA processor (400 balls, 0.8mm pitch) and a DDR3 chip in an 8-layer-PCB. I have some questions regarding of PCB.

The first one is stackup. I learned from some documents that it is ideal to use symmetric stackup in this kind of high speed design. Previously, I planed to use the stackup as: L1(signal), L2(GND), L3(PWR), L4(PWR), L5(signal), L6(signal), L7(GND), L8(signal). So, the signals on both layer 6 and layer 8 can be referenced to layer 7(GND), and signal on layer 1 can be referenced to layer 2(GND). If I use symmetric stackup, only two signal layers can be referenced to GND. So, I want to know why and how important it is to use symmetric stackup.

The second question is about impedance. I asked our PCB manufacturer to calculate trace width. The result is: single ended track for 40 Ohm should be 0.2 mm wide on outer layers, and 0.5 mm on layer 5. Differential tracks for 80 Ohm should be 0.175 mm wide on outer layers, and 0.203 mm wide on inner layers. Compared with reference design of iMX6 from FEDEVEL, I feel that the tracks are too wide. So, my questions is: is there anyone who used such wide tracks for DDR signals?

My last question is about vias. Considering PCB manufacturing cost, I plan to use through-hole vias only in my PCB, and the minimun via size is 0.4mm/0.25mm. Again, I noticed that there are a lot of uVias in iMX6 reference design. While the good thing to me is there is only one DDR3 chip on our PCB. So, I am wondering if it is possible to finish the connection between processor and only one DDR3 chip with this type of through-hole vias.

Hope someone can give me some suggestions.
Thanks in advance!