DDR II SDRAM PIN ASSIGNMENTS

[robertferanec]

Then I am not really sure what the problem can be Maybe you have already sorted it out

[mohsin_qau]

Yes Sir. I got ur point now. Yes i have matched the length according to the given diagram.

[robertferanec]

I am not sure what you mean by "I perform Length matching based on differential clock."

Do you do something like this: https://www.fedevel.com/welldoneblog...atching-rules/

The picture is for DDR3, but it is similar for DDR2. Check out especially the DATA BYTES (yellow and green block) - you need to have your databanks length matched correctly. And because your UDM and LDM signals were swapped, I am just pointing out, that they may be length matched according to different data group.

[mohsin_qau]

I perform Length matching based on differential clock.

[robertferanec]

Did you match all the data signals (data, strobe, mask) to the same length? Or you length match them based on banks?
I am asking as I am trying to understand if the signals are correctly split into databanks.

[mohsin_qau]

In the FPGA Code.Yes sir, Data bus, Data Strobe & Mask pins lengths are matched.

[robertferanec]

How did you swap the pins, in your FPGA code or on the board? Also, how the length matching is done (when you swapped the UDM & LDM, is the data bank length matching correct)?

[mohsin_qau]

Yes sir. with pin swapping......fitter error is removed. Now i run Memory test through NIOS processor. We are using Altera CycloneIII 484 BGA FPGA. But the test fails at the inital address. Can u have any experiencing with that?

[robertferanec]

So, when you swapped UDM & LDM, it now works?

[mohsin_qau]

Sir, with your effort, problem is resolved with pin swapping of UDM & LDM.

[mohsin_qau]

I have assigned FPGA Bank 7 for DDRII_D0-D7, DDRII_LDQS, DDRII_UDQS, DDRII_UDM & DDRII_LDM..........& Bank 8 for DDRII_A0-A12, CAS, RAS,WE,CS,CKE,CK_P,CK_N,ODT & Bank Addresses.

[mohsin_qau]

Sir, Please find the DDRII Pins.

[robertferanec]

How are you connecting them to the memory chip and how did you create the BANK groups (e.g. BANK0: DDR1D0-7, DDR1_LDM, DDR1_LDQS)? UDM is upper byte (8-15), LDM is lower byte (0-7). From the screenshot which you attached it looks to me, that you may have UDM and LDM swapped - but I would need to see the chip connection.

[mohsin_qau]

Data Mask Pins are associated with Respective data bytes. But the fitter report gives failure. Schematics is attached.

[robertferanec]

Hmm, only what I can think about from schematic/layout point of view is if the mask pins are correctly grouped with associated data bytes ... I am not sure about implementation in FPGA code.