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RGMII interface with KSZ9031

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  • RGMII interface with KSZ9031

    I designed the 1G LAN port with KSZ9031, But there is a problem with getting the IP! I can just see eth0 by Iconfig command!
    RGMRX and RGMTX are lengths matched, MDIO MDC and GCLKIN in also matched together, I looked to OpenRex board, all is same as schematic, but I don't know why the chip does not work!

    Any recommend would be very helpful.

    I read something about adding delay to RX and TX CLK, up to 2ns, But I'm confusing between length matching TXs and RXs signals and also make delay on CLKs!

    I checked the OpenRex board there is no Track Delay for RGMII CLKs!

    I read also about component placement on same reference ground plane, But I see in many design nobody cares about it!
    Last edited by Via; 12-29-2017, 09:26 PM.

  • #2
    We sell OpenRex with KSZ9021RN. The KSZ9031RNXIA has some silicon issues for low temperatures (we found out that after doing some testing).

    This may help you - this is what we used during testing:
    http://www.imx6rex.com/open-rex/soft...rals/#phy_mdio

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    • #3
      Thank you for the response.

      So how can I calculate my PCB RGMII Track Length and then update TX RX clock delay?
      Also, Can you tell me which registers are in KSZ9031 for write delay on it and how ( an example of phytool will be very helpful)
      Last edited by Via; 12-30-2017, 05:29 PM.

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      • #4
        I'm worried about the connection between CPU and KSZ9031, I read ./phytool read eth0/3/2 ( just change to ./phytool read eth0/1/2) exactly 0x0022.
        When I can read the register for my PHY is mean that the clocks and RX, TX clock Tracks is well designed in PCB( as length matching and impedance match)?
        I'm under stress that this problem comes from my PCB design!!

        My RXCLK is playing between 15Mhz and 25MHZ! and my GCLKIN is also 80Mhz.

        Last edited by Via; 12-30-2017, 06:13 PM.

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        • #5
          When I can read the register for my PHY is mean that the clocks and RX, TX clock Tracks is well designed in PCB( as length matching and impedance match)?
          - No. Register access is done through MDIO interface (MDIO and MDC pins). However, you may want to play with register settings to get more info about the problem you have. Especially try to read registers to see if PHY is working oki. Also, for example you may want to try to set your PHY into 100Mb mode and check if that will help.

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          • #6
            I put the PHY into 10Mb speed with ethtool software and I see the Link Led work fine, I think that I need play with RX_delay and TX_delay register to fine tune the chip.

            About KSZ9031RNXIA I need to work with board just at room temperature, it should be OK? which test that you made with this chip? what's temperature limit for working?

            Update:
            I changed the xtal 25Mhz and worked fine!!!
            Last edited by Via; 01-02-2018, 12:50 AM.

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            • #7
              Happy new year Robert,
              So currently , Clock become stable, I had some connection and disconnection to internet.
              ​I read and write now to KSZ9031 register successfully and can also change PHY speed with phytool and check TX_CLK change between 2.5 & 25 & 125Mhz.
              ​But There is problem to get IP many times from DHCP server.
              ​I will upload the Length Match signals from Openrex and my board to see that all length is matched and same in length as OpenRex board.
              ​I just to know how to calculate 2ns Trace delay in RGMII v2.0 and then program exact value to PHY registers.
              ​Can you explain how did you find the right value for PHY registers depend on trace length? Do need to update the delays for both MAC and PHY? or just one side is enough?
              ​I have access in Debian Linux boot option to change the TX and RX delay too.

              ​KSZ9031 need 1.6ns CLK delay and in my calculation is mean 260mm track length!

              ​super confused!

              ​

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              • #8
                - The problems were visible in temperatures below -20Deg C and only for 1Gb operation.
                - I do not remember the settings which I used, but search for KSZ9031 in linux source code of other boards. You will find what settings they used - that is a good starting point.

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                • #9
                  I have a super issue with KSZ9031 on second board, everything works fine, and just have a problem with getting IP from DHCP, when I check router, router detected the chip and assigned the IP! but I cannot ping the IP that assigned, another board works fine with any issue!
                  I tried to change mac address too, but nothing happens!
                  Last edited by Via; 01-06-2018, 01:13 PM.

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                  • #10
                    Another board with KSZ9031 works ok?

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                    • #11
                      Yes another work great, we tested 1G datarate too!

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                      • #12
                        So, maybe it is something wrong with the specific board (?).

                        I would try more boards ... and definitely I would do a lot of extensive testing, including running the boards in environmental chamber using temperatures between -40 to 60/80 Deg Celsius

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                        • #13
                          No any difference, I checked in details.
                          OK, so I decided to make another board but need to know how I can calculate 1.5 ns track delay. I want to know the clk track must how long than data track to make delay for RGMII requirment
                          Do you know any reference for that?

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                          • #14
                            I do not remember all the details, but I think originally you had to add delay into PCB, but then they improved RGMII specification and it doesn't require PCB delay anymore. I believe, delay is done directly on silicon level or can be set in registers. If you like, double check that with the chip manufacturer or check the reference boards.

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