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Hello there,
this is my first time in this forum so here it goes.
I am currently working on a project with STM32F4 MCU and the following SDRAM( W989D2DBJX6I @ 166 MHz) and NAND flash (MX30UF4G16AB-XKI) memories .
Everything is running at 1,8 V
The Board Stackup is as follow:
L1 Signal
L2 Vcc
L3 Signal
L4 Signal
L5 Vss
L6 Signal
Now, due to space constraints the SDRAM and Flash are placed quite close to the MCU and therefor each other.
Longest net from Flash is around 56mm and from SDRAM 37mm. I also added series resistors close to the MCU for both Data and Add Bus .
So the issue is: I was able to match the length from NAND memorywithout much troubles. But the SDRAM since its so close to the MCU and due to its orientation the Data Lines 16..31 became quite short(~20mm) compared to the rest of the bus nets. This nets are not shared with the NAND flash.
I was able to match the length by bringing the signals to L1 (upper Signal layer) and add some accordeons("zigzags") but I am afraid that this might bring more issues than benefits. Specially being one of the outside layers.
The board layout is pretty much finished, just this issue remains. I know the best would be to start the routing from the SDRAM from zero by perhaps change the component orientation to vertical , but that would mean redo mutch of the work :-(.
What would you recommend in such situation?
Much appreciated for your help.
Regards,
Pedro
this is my first time in this forum so here it goes.
I am currently working on a project with STM32F4 MCU and the following SDRAM( W989D2DBJX6I @ 166 MHz) and NAND flash (MX30UF4G16AB-XKI) memories .
Everything is running at 1,8 V
The Board Stackup is as follow:
L1 Signal
L2 Vcc
L3 Signal
L4 Signal
L5 Vss
L6 Signal
Now, due to space constraints the SDRAM and Flash are placed quite close to the MCU and therefor each other.
Longest net from Flash is around 56mm and from SDRAM 37mm. I also added series resistors close to the MCU for both Data and Add Bus .
So the issue is: I was able to match the length from NAND memorywithout much troubles. But the SDRAM since its so close to the MCU and due to its orientation the Data Lines 16..31 became quite short(~20mm) compared to the rest of the bus nets. This nets are not shared with the NAND flash.
I was able to match the length by bringing the signals to L1 (upper Signal layer) and add some accordeons("zigzags") but I am afraid that this might bring more issues than benefits. Specially being one of the outside layers.
The board layout is pretty much finished, just this issue remains. I know the best would be to start the routing from the SDRAM from zero by perhaps change the component orientation to vertical , but that would mean redo mutch of the work :-(.
What would you recommend in such situation?
Much appreciated for your help.
Regards,
Pedro
It is very hard to say - the layout may work just fine (depends how it looks). Normally, I would try to avoid to go into this kind of situation from beginning, now it may be hard to try to improve it.
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