6L or 8L Board Stackup

[qdrives]

I am currently working on a 6 layer board with the following stack-up: Sig-Gnd-Sig Sig-Gnd-Sig. In a sense, two three layers boards with a wider space in between.
It is not for high speed digital, but mostly power signals (hence the 2oz copper).
Power is routed.

[robertferanec]

That stackup is not the best. I would not use it. Exactly as you pointed out, the distances between layers are not great.

[milos.stankovic]

Hello!

I am designing the 6L board with not very big component density. It has 300-pin BGA microcontroller with SPI port and JTAG port for programming. I am taking into account maximum rising time of 1ns, although datasheet for microcontroller does not mention it specifically. I nevertheless length matched both SPI and JTAG port on L1 and L3 separately, although I think they would work even without being length match. There is also CAN bus on the board. We normally produce our boards at JLPCB, but their 6L impedance controlled stackup is not good enough, I think (attachment). I watched video which Robert made with Rick Hartley (https://www.youtube.com/watch?v=52fxuRGifLU) and I think that PWR/SIG layer 4 is way to close to L3 routing layer and to much away from L5-GND layer. There will be to much interference between power supplies on L4-PWR layer and L3-Route layer. Having watched video, I am not sure if correct 6L stackup even exists, or I shoud increase number of layers to 8.