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ADVANCED PCB LAYOUT - LESSON 7 - TROUBLE IN FINE TUNING DIFFERENTIAL PAIRS

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  • ADVANCED PCB LAYOUT - LESSON 7 - TROUBLE IN FINE TUNING DIFFERENTIAL PAIRS

    Good evening Robert, as you suggest i post here also for other people. i'm doing some practice in Lesson 7 of Advanced PCB Layout Course, now with USB1 differential pairs lenght matching.

    during lenght matching of each segment on every layers, and it seems, for my eyes and experience, correctly matched but Altium report rules violation.
    I've checked for superimposed segment or mismatch in vias/pads center also but i can't find any difference.
    I've attached some image that shows my activities, and values, during lenght matching USB1 and, of course, lenght in L1, L2, L11 and L12 are exactly the same and checked it also so in pics there are only L3 and L10.

    Then i'm moving to DIFF100 class and i see same rule violation during HDMI_CLK lenght matching, for each layers.
    I've checked and re-checked all the traces in each layers but nothing seems wrong, or i can't see it...
    So i decided to delete all traces already routed and check if Altium reports difference, and there are!
    As you can see in attached imag there are no tracks primitives and the vias are the same, because i think, or i suppose, that Altium still showing lenght in vias, but layers stack are exactly symmetrical and the number and type of vias used for N and P signals are the same.

    Finally i've had my last trying with CLK1 signals, still in DIFF100, and i'm getting weird behaviour of Altium again.
    I've attached the pics also and it's clearly visible that for each layers, except in L10, the lenghts for P and N signals are almost the same (in L3 there are 0.021mm small difference).
    So in L10 N signal are 6.056mm and P signal are 5.621mm, BUT IF I INCREASE the N signal from 6.056mm to 6.767mm Altium tell me that i've matched correctly.... and violation disapper!
    I really can't understand what's going on here...
    Could you help me to understand what is going wrong?

    All files are attached and separated for signals type inside a .ZIP archive where there is PcbDoc also for Altium directly check.

    Regards,
    Luca
    Attached Files

  • #2
    There are differences in how each AD version calculates length. Have a look at my screenshot

    In my case, Altium has different numbers in Routed length as in your case. Also notice Signal length - which should be the true electrical length, however Altium clearly has a problem with USB1_N - can not recognize the path.

    This is reason why we do not upgrade Altium every single time there is a new one - because they keep changing it. You may need to figure out by yourself what exactly the problem is in the specific altium version what you are using. Sometimes re-drawing the signal may help - or maybe try to open it in different altium version if that will show something else (?) We also keep having problems with this.


    Click image for larger version

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    Click image for larger version

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    • #3
      Hi Robert, thanks for fast reply.
      I know that Altium have some bug, especially the last version, infact i'm running the course in Altium 14.3.
      I'll try to open in the all project with version 17 and 19, maybe this help, i hope...
      But please, could you clarify me about the weird stuffs with CLK1 signals?? Is still Altium problem or somenthing that i do in wrong manner?
      This is what i've understand, in short:

      1 route same topologies signals in same layers (for example 3 or/and 10)
      2 match each segment of signals in every layers separately, this because each layer could be different phase velocity and final goal is to have signals "perfectly" in phase along the tracks

      If this is ok, as i hope, should i match all the signals with this kind of "weird issue" about lentght by manually?
      I mean without using Altium checking by the rule but work on excel sheet?

      Please tell me if i'm proceeding correctly in order to complete course and so on.
      I'll report as soon as possible the behaviour with different Altium version.

      Regards,
      Luca

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      • #4
        after version 15 net length tuning got a big overhaul. so your best bed (and imho most stable version is 17) works great in that version for me at least

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        • #5
          If you length match signals on every layer and they are routed same way (the length in VIAs is same), you still should be passing the total length rule. Is this what you mean?

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          • #6
            Originally posted by robertferanec View Post
            If you length match signals on every layer and they are routed same way (the length in VIAs is same), you still should be passing the total length rule. Is this what you mean?
            Yes i mean in every layer and also each layers, for example:
            L1 - same lenght - starting point (uP)
            L3 - same lenght - travelling signals
            L6 - same lenght - traveling signals
            L8 - sane lenght - end point

            So not only the sum of lenght (total lenght) are matched but every traces for each layers are matched.

            For Paul, i'll try in Altium 17 maybe tonight or tomorrow, i've to reinstall it again.
            Thanks for advice and we let you informed.

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            • #7
              Oki, please let us know.

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              • #8
                Good evening to everyone,
                i've just tryed with Altium 19.1.5 and Altium 17.0 and same problem
                Some suggestion for finish well this course but also in "generally speaking" for future?
                Maybe some configuration or somenthing "hided"??
                Regards, Luca

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                • #9
                  Signal length is something different as routed length. Clearly for some reason Altium does not recognize the copper connection for USB1_N and I guess it is showing just Manhattan distance between the pins. Usually, re-drawing the signal helps - need to find where exactly altium see the tracks broken. I will try it later.

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                  • #10
                    Good evening Robert,
                    i've already tryied to re-draw the signal in two ways:

                    1- just delete all the traces one by one in each layers, deleted all vias, re-draw the tracks with "differential pair" routing mode.
                    2- deleted all the traces by selecting each net and used "unroute net" command, re-draw the tracks with "single track" routing mode.

                    For both methods i've had the same result in A19 and A17.

                    I'm in contact with Altium support for this specific problem.
                    Meanwhile thanks for your time for trying to find what could be the bug.

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                    • #11
                      The forum was down for a few days, Luca any updates on this?

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                      • #12
                        Good evening Robert, i've seen and i'm glad that you have restored everthing now!
                        Unfortunately i don't have any news about this Altium behaviour. Next week i'll ask again at support.
                        Can you give me and idea, or your ways that you would like to do, in order to complete the course if i can't solve this issue?
                        Please let me know ASAP because at the moment i'm blocked at this lesson.
                        Regards,
                        Luca

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                        • #13
                          You can continue normally.

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