Back Drilled Vias and Dielectric Constant
ahmad , 10-16-2019, 07:08 PM
Hi Robert,
I just have a few questions about your openRex PCB stackup.
You have used through-hole Vias in this PCB. As you mentioned in your course, we shouldn't have any stub in our DDR3 routing.
I'm just wondering if you have used back drilled vias to remove the stubs?
According to the manufacturing process, do we need to give a manufacturer drilling document for back drilled vias as well? This part is not clear to me!
Do we need to implement back drilled vias for power line and GND as well or it is just necessary for signals?
for example, if I need to connect Layer 2 GND to Layer 9 GND with vias, to create a current path for some signals, should it be back drilled vias? or it doesn't matter?
I have a question about dielectric constant as well, In different core and prepreg materials, they have given different dielectric constant for 100MHZ, 1 GHZ and 10GHZ. In our case do we need to use the 1GHZ dielectric constant? What about the manufacturers, do they calculate the impedances by using 1GHZ dielectric constant or other values?
Who is your PCB manufacturer? Exception PCB solution? Have you ever worked with any Chinese manufacturer? American or European companies are too expensive
I would appreciate your time if you can answer these questions.
I'm looking forward to hearing from you.
Kind Regards,
Ahmad.
I just have a few questions about your openRex PCB stackup.
You have used through-hole Vias in this PCB. As you mentioned in your course, we shouldn't have any stub in our DDR3 routing.
I'm just wondering if you have used back drilled vias to remove the stubs?
According to the manufacturing process, do we need to give a manufacturer drilling document for back drilled vias as well? This part is not clear to me!
Do we need to implement back drilled vias for power line and GND as well or it is just necessary for signals?
for example, if I need to connect Layer 2 GND to Layer 9 GND with vias, to create a current path for some signals, should it be back drilled vias? or it doesn't matter?
I have a question about dielectric constant as well, In different core and prepreg materials, they have given different dielectric constant for 100MHZ, 1 GHZ and 10GHZ. In our case do we need to use the 1GHZ dielectric constant? What about the manufacturers, do they calculate the impedances by using 1GHZ dielectric constant or other values?
Who is your PCB manufacturer? Exception PCB solution? Have you ever worked with any Chinese manufacturer? American or European companies are too expensive
I would appreciate your time if you can answer these questions.
I'm looking forward to hearing from you.
Kind Regards,
Ahmad.
Paul van Avesaath , 10-17-2019, 12:01 AM
Okay I am not robert, but here's my 2 cents..
Do we need to implement back drilled vias for power line and GND as well or it is just necessary for signals? -> NO
you want to minimize stubs in your DDR3, but that is not always possible. in most cases making the sub as small as possible will be enough.
back drilling is the worst becaus you need much larger clearances around your via's and leave te bottom clear of components to do so.
also it is a very tricky process. lots can go wrong.
For ddr3 backdrilling is NOT an option and it is better to us a combination of blind and buried via's if needed.
but if your design is not exeeding 533Mhz clock speed then you can go with through hole via's and try to keep stubs to be as small as possible.
for reference I have designs upto 800Mhz that worked fine.. but i did feel uncertain about it. (the design was intended to run at slower speed) but hey.. if faster works then go for it..
if you are making a design that goes in to high volume production i would advise that you do a post layout simulation. this way you can go to mass production with ease of mind and the cost of simulating will be negligible, because you can go with cheaper production methods.
gnd via's are best done in full through hole.
about the dielctric constant yes there are differences but these do not influence that much in this case..
play around with the numbers in saturn PCB and see what happens.. e.g.
er = 4,6 (default FR4) then conductor impedance is 84.7586 ohm = 84
er = 4.2(FR4-HR+) then conductor impedance is 87.9526 ohm = 87
if you are implementing " controlled impedance" it is usually @ 10%.. so for a 50 Ohm line you are expecting to be at 45-55 ohm with you trace.
so even if you pay for it you will get a differences..
also usually the er between prepreg and core do not differ that much to be of heavy influence.
hope this helps..
Do we need to implement back drilled vias for power line and GND as well or it is just necessary for signals? -> NO
you want to minimize stubs in your DDR3, but that is not always possible. in most cases making the sub as small as possible will be enough.
back drilling is the worst becaus you need much larger clearances around your via's and leave te bottom clear of components to do so.
also it is a very tricky process. lots can go wrong.
For ddr3 backdrilling is NOT an option and it is better to us a combination of blind and buried via's if needed.
but if your design is not exeeding 533Mhz clock speed then you can go with through hole via's and try to keep stubs to be as small as possible.
for reference I have designs upto 800Mhz that worked fine.. but i did feel uncertain about it. (the design was intended to run at slower speed) but hey.. if faster works then go for it..
if you are making a design that goes in to high volume production i would advise that you do a post layout simulation. this way you can go to mass production with ease of mind and the cost of simulating will be negligible, because you can go with cheaper production methods.
gnd via's are best done in full through hole.
about the dielctric constant yes there are differences but these do not influence that much in this case..
play around with the numbers in saturn PCB and see what happens.. e.g.
er = 4,6 (default FR4) then conductor impedance is 84.7586 ohm = 84
er = 4.2(FR4-HR+) then conductor impedance is 87.9526 ohm = 87
if you are implementing " controlled impedance" it is usually @ 10%.. so for a 50 Ohm line you are expecting to be at 45-55 ohm with you trace.
so even if you pay for it you will get a differences..
also usually the er between prepreg and core do not differ that much to be of heavy influence.
hope this helps..
robertferanec , 10-17-2019, 08:59 AM
Just would like to add to @Paul van Avesaath 's answer
- I have never used backdrilled VIAs even on DDR3 and everything was always working ok (but you may want to keep stub in VIA at minimum). I have seen even very fast interfaces routed with stub in VIA - and working just fine. So, for standard designs, I am not sure if I would be worried about backdrilled VIAs - unless reference design is using them. I am not even sure if the server board what I was reviewing used backdrilleld VIAs: https://www.youtube.com/playlist?lis...3yeEbwVsNGU4jY
- Normally I do not tell manufacturer to use specific frequency for impedance calculation, but if you go above 5GHz, you may want to tell them.
- Yes we normally use Exception PCB, they are in the UK, but everything is now manufactured in China anyway. So, the prices are ok.
- I have never used backdrilled VIAs even on DDR3 and everything was always working ok (but you may want to keep stub in VIA at minimum). I have seen even very fast interfaces routed with stub in VIA - and working just fine. So, for standard designs, I am not sure if I would be worried about backdrilled VIAs - unless reference design is using them. I am not even sure if the server board what I was reviewing used backdrilleld VIAs: https://www.youtube.com/playlist?lis...3yeEbwVsNGU4jY
- Normally I do not tell manufacturer to use specific frequency for impedance calculation, but if you go above 5GHz, you may want to tell them.
- Yes we normally use Exception PCB, they are in the UK, but everything is now manufactured in China anyway. So, the prices are ok.
ahmad , 10-17-2019, 03:38 PM
Hi Guys,
Thanks for your inputs.
As I've seen in iMX6Q-SABRE-SDB and i.MX6QP_SABRE_AI evaluation boards, They didn't use any blind or micro vias. Even in OpenRex board design, all vias are through holes and probably without back drilling as Robert point it out.
I'm just wondering if in NXP iMX6 evaluation board they have used back drilled vias to minimize the stubs?
Could you please clarify this for me?
Thanks for all your help.
Thanks for your inputs.
As I've seen in iMX6Q-SABRE-SDB and i.MX6QP_SABRE_AI evaluation boards, They didn't use any blind or micro vias. Even in OpenRex board design, all vias are through holes and probably without back drilling as Robert point it out.
I'm just wondering if in NXP iMX6 evaluation board they have used back drilled vias to minimize the stubs?
Could you please clarify this for me?
Thanks for all your help.
robertferanec , 10-21-2019, 05:33 AM
iMX6 doesn't need back drilled VIAs - it doesn't have so high speed interfaces.
ahmad , 10-21-2019, 06:04 PM
Thank you, Robert.
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