Stack-up doubts: Track thickness + Copper filling percentage

[gmezzina23]

Hi guys,

I was checking the spreadsheet available here https://welldoneblog.fedevel.com/201...your-projects/

In the Impedance Requirements table, it says "Please, use maximum SE55 track thickness on L1 & L6 < 6mil (0.15mm)".
What means "track thickness" in this context? Does it mean the thickness of the layer foil or the track width (and it is simply a typo)? (In the suggested stack up, the thickness is set 0.5 oz on L1)

I was also checking the Stackup n. 6 here (https://welldoneblog.fedevel.com/201...your-projects/)


What does it mean with "% of copper in layout"? Why 90% is selected?


Sincerely,
GM

[robertferanec]

- % of copper is how much surface is covered with copper and how much is without copper. That can for example influence the final thickness of prepreg (during PCB manufacturing prepreg melts and it goes between tracks - so if less surface has copper, thinner the final thickness will be)

- Hmm .. I only see pdfs, I can't find what spreadsheet you mean, but it looks more like a typo and should be probably width.

[gmezzina23]

Dear Robert,

first of all, thank you for your reply.

- Hmm .. I only see pdfs, I can't find what spreadsheet you mean, but it looks more like a typo and should be probably width.

For sake of completeness, please find attached the "incriminated" spreedsheet @step4 in https://welldoneblog.fedevel.com/201...m-pcb-stackup/

Sincerely,
Giovanni

[robertferanec]

Dear Giovanni, yes, it's a typo, should be width.