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  • SPI Layout

    Hello, I have to design the DAC board with the SPI interface the clock is about 200MHz with 4 peripheral. I like to use star topology for the design, but I confuse about how to do length matching and impedance matching for this work since it seems to have some split node between track (MOSI, SCLK, SS). Could you guys please give me a suggestion. Thanks.

  • #2
    For 200MHz split between 4 peripherals I would maybe consider using buffers or multiplexers.

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    • #3
      Thank you, Robert. For using buffers, you mean clock buffer like this https://www.onsemi.com/pub/Collateral/NB3L553-D.PDF?



      Last edited by Tanachai Limpisawas; 03-02-2020, 10:37 AM.

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      • #4
        Yes, for example like that.

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        • #5
          I got it. Could you suggest more about when to prefer clock buffers over star routing (how many peripherals, how much frequency, etc. ). Thank you for your help.

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          • #6
            I am not sure if there is a clear rule to specify when to use buffers, however in this specific case I suggested it as you have 5 chips connected together and it is safer to use "4 individual" connections as trying to balance (and possibly simulate) a proper way to do layout of situation when all the 5 chips are connected directly together and running at 200MHz.

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