DDR3 routing (with xilinx zynq chip as driver)

[luigi]

Board setup:

XC7Z020-1CLG400C zyng as driver

IS43TR16256A-125KBL as DDR3

1. Question:

What is better to routing (ADDRESS + CONTROL) signals

a. Some in one layer (with tracks only in this layer) and some others in an other signal layer (with tracks only in this layer);

Example

PIN1 -> VIA -> L3 -> VIA -> PIN2

PIN3 -> VIA -> L8 -> VIA -> PIN4

b. In 2 layer with track segment in both layer;

Example

PIN -> VIA -> L3 -> VIA -> L8 -> VIA -> PIN;

all lines routed in this way.

Thanks a lot

[robertferanec]

b is safer (that is also what I prefer to use). In some cases we do route add/cmd/ctl signals on different layers, but then you need to know what you are doing - you need to be careful about proper length matching.

[luigi]

Hi,

before all thanks a lot Robert.

I'm routing ADDR/CMD/CNTR tracks group.
How much has to be the difference lenght between track in this group, before tuning?
In my routing I have 20 mm difference between longer track and shorter. In this way I have to use big space to tunning tracks.
Is it right or I have to change the base routing?

Thanks

[robertferanec]

I usually have three phases:
1) connect - in this phase, there may be big difference between tracks, still, be sure difference is not too big as it may be very difficult to add a lot of length on many signals.
2) do approximate length matching (almost the right length, but not spending too much time playing with it) - often I make the tracks a little bit longer as it is simple to make them shorter
3) fine tuning (final length matching and locking down the tracks) - adjusting the tracks to the target length.

So it depends in what phase of design you are ... in phase 1 you may have 20mm difference.

[luigi]

Hi Robert,

I'm in first phase.

Thanks a lot

Luigi