Lesson 7 (Advance Hardware Design) - CPU fanout and memory routing
schad.rio , 03-29-2020, 11:27 PM
Was practicing the memory layout exercises and had a question: For DDR_DATA_BANK2, I do not see the corresponding nets for the data signals on the memory modules. I see the DRAM_xx nets on the CPU but do not see DRAM_16 to DRAM_23 on any of the memory modules. I checked both top and bottom layers. This is probably something simple but am I missing something? I would expect to see these data signals on both the CPU and memory modules, as they were on DDR_DATA_BANK0 and DDR_DATA_BANK1. I currently using using Altium 20.0.9, using the Lesson 7 files (VOIPAC iMX53 DDR Layout - EASY). See attachment.
robertferanec , 03-31-2020, 06:55 AM
It was intentionally removed as VOIPAC didn't want us to share too much from the design.
schad.rio , 03-31-2020, 08:31 AM
Got it. Thanks. Is it possible to put in the lesson a note to ignore these banks or remove these banks from the PCB files? I spent considerable time trying to figure out what I was doing wrong.
robertferanec , 04-02-2020, 06:00 AM
Thank you for feedback. I apologize. I will be more careful in next course about this.
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