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Calculating Impedances using Altium Stackup Manager (Lesson 4 of APLC)

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  • Calculating Impedances using Altium Stackup Manager (Lesson 4 of APLC)

    Hi Robert,

    I'm working through Lesson 4: High Speed of "Advanced PCB Layout". In that lesson, you requested a stackup from your PCB Vendor which supplied the track widths and separations needed to maintain the impedances you requested (55 ohm SE, 90 ohm DIFF, and 100 ohm DIFF). You then manually entered these into the Altium design rules. You also showed us how to use a tool from "Saturn PCB" to estimate these impedances given the stackup details.

    The Altium Stackup Manager not only allows you to define the stackup, but you can also create impedance profiles for various SE and DIFF impedances. Similar to the Saturn tool, this capability allows you to experiment with the stackup and track dimensions to estimate impedances. Since it directly references the stackup information and has a direct connection to the Altium Design rules, it can be much more automated and error-proof than the Saturn tool.

    I have attached a snap-shot of the Layer Stack Manager showing one of the impedance profiles (100ohm differential - "D100") I created using the track width and spacing numbers supplied by your PCB vendor. I was curious to see how the Altium results compared to your vendors results and also to the Saturn tool, so I documented the results for all three profiles, from all three tools, in the attached table. There were some results from the Altium tool which didn't match well with the numbers from the vendor or the Saturn tool (see highlighted items in table).

    Altium claims that they have spent a lot of effort on the "field solver" which calculates these impedances. Have you had experience using their tool to calculate impedances? Do you trust their results?

    Thank you!

    Click image for larger version

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    Attached Files

  • #2
    Like all calks it is not as good as fabrication, but (But) simbeor , like hyperlinks does only what it is set to do. May me dielectric was thinner, may be coating of was not calculated
    But I have done some boards using PolarSi9000 to calculate traces and checked it in hyperlinks they were fine, but Saturn pcb was a bit off, but still in 6% tolerance. Manucatured pcb showed almost same parameters. Last month I checked it with new stackup manager and it was fine.

    From what i see top and bot layers have no galvanic copper on it in the stackup. For 35micron foil it should be almost 60 microns after via plating. so traces will be thicker than you calculated. same for diff pairs. That's why inner layers are fine.


    • #3

      Are you suggesting that the outer two layers in my Altium stackup do not include plating? I have attached the Polar data from Robert's class to this post. L1 and L12 show a base thickness of 0.012mm, but a "finish" thickness of 0.035. I believe the "base" thickness is the thickness of the foil, and the "finish" thickness includes the plating. In the Altium model, I used the "finish" thickness. Does that sound valid?
      Click image for larger version

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      • #4
        Yes, that sound valid. Let's keep looking. There should be reason why difference on top and bot layers are so drastic.
        BTW solder mask Dk is around 3.45.


        • #5
          This is so nice! Thank you Tom Yunghans for doing this.

          PS: No, I do not use Altium for impedance calculation. But I heard, they keep improving it, so let's see what will happen.


          • #6
            I recently attended a free 2 hour training session from Altium on High Speed design, where he discussed using the impedance profile capability. I diverted from the Advanced PCB Layout class to test out this feature on the Rex Processor Module. I am currently discussing this issue with the person from Altium that made that presentation, his name is John Magyar. I will post here when I hear back from him.


            • #7
              It's an interesting comparison, but I think I've catch something there.

              You're using 4.3 for the Saturn tool calculations, which makes sense for L3-L10 since they have 4 and 4.6 dielectric around them, but L1-L12 don't. A lower constant on them would increase the impedance, so at least the delta is on the right direction (I don't know if it covers all the difference).

              I tried to replicate some of the saturn results without much success (I admittedly didn't try too hard), could you share all the parameters to play with the numbers a bit?


              • #8
                The stackup entered into the Altium Layer Stack Manager shows a dielectric constant of 4.0 for the dielectric between L1 and L2 and between L11 and L12. So that is what I used in the Saturn tool when calculating the differential pair microstrip impedance for L1 and L12.. Here is a snap-shot of that calculation, with the nominal differential Z coming out very near 100 ohms (compared to 111.37 calculated by the Altium field solver).

                Click image for larger version

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                • #9
                  Issue is that in saturn PCB you do not include soldermask, but real life manufacturer includes it in calculation, so altium does. Dk for soldermask is close to epoxy Dk and is around 3.45 ( 3.3 to 3.6 what I have seen and used). So, basically you are using wrong model of trace in Saturn.
                  Click image for larger version

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                  This is more likely to be true.

                  Sorry, I couldn't lay my hands on Polar SI9000, yet.
                  Attached Files


                  • #10
                    Hello Tom Yunghans ,

                    Altium introduced the Impedance calculations in their latest versions and from my latest 3 design the manufacturer data of impedance profile matches with Altium impedance calculator as you have shown above..
                    Will be interesting to see what the atlium support tell you about this..

                    Thank you.


                    • #11
                      Hi Beamray,

                      I initially thought about using the "Edge Cpld Embed" capability in Saturn to include the solder mask, but as an experiment I deleted the solder mask from the Altium Layer Stack Manager, and still got the same number (111.37ohms). I was a little surprised by that, as I would have though it would have made some difference. Maybe this is another question for Altium? Therefore, I concluded that the Altium field solver didn't take the solder mask into consideration so I left it out of the Saturn model.

                      I was surprised by your calculations when you included the solder mask using the "Edge Cpld Embed" model in Saturn. My initial impression was that including a dielectric other than air above the copper would lower the impedance, not raise it (the calculation you performed showed it going from 101 to 105). I looked at the numbers in your calculation and I believe the number you entered for H2 is too small. H2 needs to be H1+copper thickness+solder mask thickness; in this case 0.075+0.035+0.02=0.13. When I entered 0.13 for H2, I get 97 ohms, slightly smaller than the original 101 ohms I calculated without the solder mask. For the dielectric constant of the dielectric, I continued to use 4. The stackup from the PCB vendor specified the prepreg below the copper as 4.0 and the solder mask dielectric as 4.1. Since the prepreg is about 4x thicker than the solder mask (0.075 vs 0.02), I figured it would dominate. I have attached those Saturn results below.

                      Click image for larger version

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                      • beamray
                        beamray commented
                        Editing a comment
                        You are right. My mistake

                    • #12
                      Tom Yunghans Never the less you have something wrong with your AD.
                      I Just tried it on my board (20.1 AD)
                      Original board (almost perfectly matched with real one)
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                      Little variation with thicker soldermask
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                      And No mask
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                      I think, Altium guys add something and have broken something else as they usually do. May be try update to 20.1
                      BTW in 20.1 length matching again works a bit differently.

                      I think we should find some way to model it in CST or, AWR and in Hyperlynx.
                      I always double check AD with SI9000 (but I do not have one anymore).
                      Attached Files


                      • #13
                        I think, Altium guys add something and have broken something else as they usually do.
                        - that is reason why I do not fully rely on AD features in critical parts of design such impedance or length matching. They are very inconsistent between AD versions and it is too dangerous to fully trust these features.