DDR3 Memory Data Buses
kazemiy974 , 06-14-2020, 08:10 AM
Hello All;
I have a question from schematic design of ddr3 memory.
I'm designing a board based on Allwinner H3 chip,and i decided to have a look to Orange Pi One schematic because it's Cpu is Allwinner H3 chip.
in section of ddr3 memory i found a new confusing issue and it is ddr3 data buses.I attached a image file it shows ddr3 schematic design,why aren't the names in the SDQ nets in order?can we design the data section in ddr memories as we wish? just swap nets with each other?if this is true, i have no justification for it😟
I have a question from schematic design of ddr3 memory.
I'm designing a board based on Allwinner H3 chip,and i decided to have a look to Orange Pi One schematic because it's Cpu is Allwinner H3 chip.
in section of ddr3 memory i found a new confusing issue and it is ddr3 data buses.I attached a image file it shows ddr3 schematic design,why aren't the names in the SDQ nets in order?can we design the data section in ddr memories as we wish? just swap nets with each other?if this is true, i have no justification for it😟
grrmachine , 06-14-2020, 03:59 PM
Hi @kazemiy974
As most of the DDR3 chips come in BGA packages and often it's tricky to route signals. Hence chip manufacturers/JEDEC provisioned data bit/byte swapping. This is valid only to the data (DQ) signals.
1) DQ signals can be swapped within a data byte.
2) Bytes group can be swapped, all signals DQ, DQS, DM have to be swapped.
Note that the DQ signal cannot be swapped between data bytes.
Eg DQL0 can be swapped between DQL1-DQL7 and not with DQU0-DQU7.
If data bytes are swapped connect the relevant data mask (DM) and strobe (DQS_N, DQS_P) to the appropriate data byte group, also DQS signals cannot be swapped within the differential pair.
Find out more about this from the memory manufacturer or DDR design guides.
As most of the DDR3 chips come in BGA packages and often it's tricky to route signals. Hence chip manufacturers/JEDEC provisioned data bit/byte swapping. This is valid only to the data (DQ) signals.
1) DQ signals can be swapped within a data byte.
2) Bytes group can be swapped, all signals DQ, DQS, DM have to be swapped.
Note that the DQ signal cannot be swapped between data bytes.
Eg DQL0 can be swapped between DQL1-DQL7 and not with DQU0-DQU7.
If data bytes are swapped connect the relevant data mask (DM) and strobe (DQS_N, DQS_P) to the appropriate data byte group, also DQS signals cannot be swapped within the differential pair.
Find out more about this from the memory manufacturer or DDR design guides.
Tom Yunghans , 06-14-2020, 06:46 PM
Hello,
The concept of bit swapping in a RAM interface is not new, but has become more valuable as interfaces became faster and the layout more critical (e.g. the need for length matching and avoiding the use of vias). This works because it doesn't really matter what bit in the RAM is used for storing each processor data bit, as long as it gets read back using the same approach as it was written. This also can work for parallel non-volatile parts (e.g. NOR or NAND), but in that case, if you wrote the device before putting it on the board, you need to write the data so it gets read properly.
As grrmachine points out above for DDR memory, bit swapping can only be done within a byte lane, but you can also swap an entire byte lane with another byte lane. However, if you do that, you must not only swap the data lines, you must also swap the "mask" and the "strobe" lines that are associated with each byte lane.
The concept of bit swapping in a RAM interface is not new, but has become more valuable as interfaces became faster and the layout more critical (e.g. the need for length matching and avoiding the use of vias). This works because it doesn't really matter what bit in the RAM is used for storing each processor data bit, as long as it gets read back using the same approach as it was written. This also can work for parallel non-volatile parts (e.g. NOR or NAND), but in that case, if you wrote the device before putting it on the board, you need to write the data so it gets read properly.
As grrmachine points out above for DDR memory, bit swapping can only be done within a byte lane, but you can also swap an entire byte lane with another byte lane. However, if you do that, you must not only swap the data lines, you must also swap the "mask" and the "strobe" lines that are associated with each byte lane.
kazemiy974 , 06-15-2020, 06:07 AM
Thanks a lot @grrmachine .
If I use memory that has 16 data lines i can swap data bits between SDQ0 and SDQ15?What is the advantage of this 16bit memories?and is it different to use them in different situations?
If I use memory that has 16 data lines i can swap data bits between SDQ0 and SDQ15?What is the advantage of this 16bit memories?and is it different to use them in different situations?
kazemiy974 , 06-15-2020, 06:14 AM
Thank you so much @Tom Yunghans .
I realize that I could swap data in just one byte or each 16bits.Is it true?and can i swap each bytes or each 16bits to each other?
I realize that I could swap data in just one byte or each 16bits.Is it true?and can i swap each bytes or each 16bits to each other?
Tom Yunghans , 06-15-2020, 07:43 AM
If it is a chip with a 16 bit interface, a single DM line and a single clock pair, then I would think it shouldn't be a problem to swap any of the 16 data bits with each other.
The chip you showed the schematic for looks like a 16 bit chip which contains two 8 bit interfaces, each with their own DM and clock strobe pairs. In that case you can swap within each 8 bit group or you could swap the two 8 bit groups with each other. All 8 bits from each group would have to be swapped with the 8 bits from the other interface, including the respective DM and data strobes.
In fact, with your two chip scenario implementing a 32 bit interface, you should be able to swap byte lanes between chips. For example if chip 1 originally had bytes 0/1 and chip 2 had bytes 2/3; you could swap byte lanes so that chip 1 had bytes 0/3 and chip 2 had bytes 3/2, or other combinations.
However, always check your datasheet and design guides carefully.
The chip you showed the schematic for looks like a 16 bit chip which contains two 8 bit interfaces, each with their own DM and clock strobe pairs. In that case you can swap within each 8 bit group or you could swap the two 8 bit groups with each other. All 8 bits from each group would have to be swapped with the 8 bits from the other interface, including the respective DM and data strobes.
In fact, with your two chip scenario implementing a 32 bit interface, you should be able to swap byte lanes between chips. For example if chip 1 originally had bytes 0/1 and chip 2 had bytes 2/3; you could swap byte lanes so that chip 1 had bytes 0/3 and chip 2 had bytes 3/2, or other combinations.
However, always check your datasheet and design guides carefully.
robertferanec , 06-15-2020, 08:53 AM
@Tom Yunghans is absolutely right. You can only swap within byte, because each byte is using it's own DQS and DQM signals.
For example, if your DQS0 is 1000mils long, simply to say, your DATA5 will need to be 1000mils long.
If you would swap your DATA5 with for example a byte using DQS1 as a strobe signal and your DQS1 would be only 500mils ... what would be the length of DATA5?
PS: In some designs you will find a note, that Lowest bit can not be swapped due some use in calibration (I am not exactly sure how it works)
PSS: This picture can give you an idea how it is lenghtmatched - but always read design guides as it is different between chips: https://welldoneblog.fedevel.com/201...atching-rules/
For example, if your DQS0 is 1000mils long, simply to say, your DATA5 will need to be 1000mils long.
If you would swap your DATA5 with for example a byte using DQS1 as a strobe signal and your DQS1 would be only 500mils ... what would be the length of DATA5?
PS: In some designs you will find a note, that Lowest bit can not be swapped due some use in calibration (I am not exactly sure how it works)
PSS: This picture can give you an idea how it is lenghtmatched - but always read design guides as it is different between chips: https://welldoneblog.fedevel.com/201...atching-rules/
kazemiy974 , 06-16-2020, 12:44 AM
Your tips were great.thanks a lot @robertferanec , @Tom Yunghans
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