Hi, Robert!
Thanks for great courses, I've just started advanced Layout course, and that's my first one. Can you please explain, why do we have such decoupling capacitors count in our lessons?
In VDDARM_CAP net there are 8 pins, and 4 0.22u capacitors with 1 bulk.
In VDDSOC_CAP - 7 pins with 6 small capacitors and 1 bulk.
If I do my own design, what is the way to the choose number of capacitors? Try to do 1 piece for every pin and sometimes group them by 2, if there not enough space?
Or is there's some topic to read which explains that?
Thanks for great courses, I've just started advanced Layout course, and that's my first one. Can you please explain, why do we have such decoupling capacitors count in our lessons?
In VDDARM_CAP net there are 8 pins, and 4 0.22u capacitors with 1 bulk.
In VDDSOC_CAP - 7 pins with 6 small capacitors and 1 bulk.
If I do my own design, what is the way to the choose number of capacitors? Try to do 1 piece for every pin and sometimes group them by 2, if there not enough space?
Or is there's some topic to read which explains that?
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