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pal , 12-08-2020, 09:23 AM

Hello
I understand that there are PCB Design guidelines for DDR2 but are there any specific guidelines for NAND & NOR Flash memory IC's nets ? i don't see its mentioned on chip manufacturer's datasheet or reference guide.
or is it by default comes under high speed design rule category and have to apply length matching rule as well as single ended and differential impedance rules like DDR2

Thanks in advanced !

jebin , 12-08-2020, 10:35 AM

Hi Pal,
Pls refer the below document link it may help you.




Jebin

pal , 12-08-2020, 11:16 AM

Thanks Jebin !

robertferanec , 12-09-2020, 07:46 AM

There are often no specific design guidelines for NAND or NOR and they are not so critical. I am not sure what frequency you are looking for, but you can find examples of requirements for "slower" interfaces in some documents. I often recommend google for "com express design guide" and you can find this (see the picture below).

From this document you can see what you need to be careful about e.g. data groups, strobe signals (read, write, etc ...) and also it can give you an idea what kind of length matching tolerance you may be aiming for.

https://www.kontron.com/download/dow...2013-12-06.pdf

pal , 12-10-2020, 03:07 PM

Thanks Robert, I will review this information - here is the freq - NAND Freq. ~40Mhz, NOR ~62.5MHz

robertferanec , 12-14-2020, 01:49 AM

Even for 60MHz you still may follow the recommendations from above. They are quite strict.

I have seen much relaxed rules ... just google for example for "pci 66MHz design guide length matching":
- https://www.intel.com/content/dam/ww...ssor-guide.pdf
- https://www.renesas.com/eu/en/docume...ign-guidelines