Hello all,
I have designed an 8 layer board, with mounted components on both sides. However, on the bottom signal layer a set of tracks (JTAG signals) is crossing the gap formed between +3.3V and +5V on layer 7.
Since we were in a hurry, I just added on both sides around the set (left and right) where it crosses the gap a mix of decoupling capacitors connected between +3.3V and +5V, in order to assure a return path for those signals. The closest GND plane is a solid plane on layer 6.
I am asking for some recommendations, also if someone has performed some simulations for a case like this, and what exactly this approach may cause to the operation of the PCB itself ?
Thanks,
Max!
I have designed an 8 layer board, with mounted components on both sides. However, on the bottom signal layer a set of tracks (JTAG signals) is crossing the gap formed between +3.3V and +5V on layer 7.
Since we were in a hurry, I just added on both sides around the set (left and right) where it crosses the gap a mix of decoupling capacitors connected between +3.3V and +5V, in order to assure a return path for those signals. The closest GND plane is a solid plane on layer 6.
I am asking for some recommendations, also if someone has performed some simulations for a case like this, and what exactly this approach may cause to the operation of the PCB itself ?
Thanks,
Max!
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