Clock Signals

[robertferanec]

- Should copers pour, connected to gnd, be placed around that signal ?

I do not do that. However, I often use 33R series termination resistor. As qdrives pointed out, I just posted a video which could be useful for you: https://youtu.be/CDJn-35W8sg

About the distortion - it looks to me, like the output is weak (what are your output clock pin settings - e.g. push/pull, open drain, weak / slow, strong / fast, etc ...) or there may be a big load on that track (?)

[qdrives]

Are the plots you shown measure with an oscilloscope on an actual board?
If so, then I do not think you need much. Of course better... keep distance, Gnd, stiching, but it takes space.
Rise time in the plots low for 6.8MHz.
Also check this latest video from Robert https://www.youtube.com/watch?v=CDJn-35W8sg

[Brunodrt]

the total length of the clk trace is 34.75mm and the width is 0.254mm . I have copper pour around the trace and a GND plane bellow (0.36mm dielectric).
On the datasheet of the SPI device there was not much information ( only information SPI Interface with Clock Speeds Up to 20 MHz)
The layout you see in the image shows it all of this spi trace. there is no termination resistor cause I didn't know I needed one ? could it help to reduce the rise and fall time ?

thank you

[qdrives]

The rise time of the signal is more important then the clock frequency.
What about termination? Total length? If the layout shows it all, then no termination is required.

[Brunodrt]

So this is the issue. Attached are the image from the same clock signal at 3 Different frequencies ( around 1.68Mhz, 3.37Mhz and 6.8Mhz) and it is visible the distortion of the signal as the frequency increases.
I've attached also the layout. The signal go from the uC to a connector. Bellow that signal layer there is a GND layer ( 4 layer Board )

what could be the cause of the distortion and what could be improved to reduce the distortion at higher frequencies ?

Thank you.

[Brunodrt]

Hello All,

what kind of things should be avoided or should be done when routing high speed signals ( in this case i'm referring to a the clock of a SPI ).
I've spaced the signal from the remaining and have a solid GND plane bellow.

My doubt is :
- Should copers pour, connected to gnd, be placed around that signal ?
- Should stitching vias be placed close to the signal ?

Thank you all.